UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 486

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
15.6.7 UART reception
1. In the reception wait status, the RXDAn pin is monitored and start bit detection is performed.
if the RXDAn pin is low level at the start bit sampling point. After a start bit has been recognized, the receive operation
starts, and serial data is saved to the UARTAn receive shift register according to the set baud rate.
UARTAn receive shift register is written to the UAnRX register. However, if an overrun error (UAnSTR.UAnOVE bit) occurs,
the receive data at this time is not written to the UAnRX register and is discarded.
continues until the reception position of the first stop bit, and INTUAnR is output following reception completion.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
The reception wait status is set by setting the UAnCTL0.UAnPWR bit to 1 and then setting the UAnCTL0.UAnRXE bit to
Start bit detection is performed using a two-step detection routine.
First the rising edge of the RXDAn pin is detected and sampling is started at the falling edge. The start bit is recognized
When the reception complete interrupt request signal (INTUAnR) is output upon reception of the stop bit, the data of the
Even if a parity error (UAnSTR.UAnPE bit) or a framing error (UAnSTR.UAnFE bit) occurs during reception, reception
Cautions 1. Be sure to read the UAnRX register even when a reception error occurs. If the UAnRX register is
2. The operation during reception is performed assuming that there is only one stop bit. A second
3. When reception is completed, read the UAnRX register after the reception complete interrupt
4. If receive completion processing (INTUAnR signal generation) of UARTAn and the UAnPWR bit = 0
RXDAn
INTUAnR
UAnRX
not read, an overrun error occurs during reception of the next data, and reception errors continue
occurring indefinitely.
stop bit is ignored.
request signal (INTUAnR) has been generated, and clear the UAnPWR or UAnRXE bit to 0. If the
UAnPWR or UAnRXE bit is cleared to 0 before the INTUAnR signal is generated, the read value of
the UAnRX register cannot be guaranteed.
or UAnRXE bit = 0 conflict, the INTUAnR signal may be generated in spite of these being no data
stored in the UAnRX register.
To complete reception without waiting INTUAnR signal generation, be sure to clear (0) the
interrupt request flag (UAnRIF) of the UAnRIC register, after setting (1) the interrupt mask flag
(UAnRMK) of the interrupt control register (UAnRIC) and then set (1) the UAnPWR bit = 0 or
UAnRXE bit = 0.
Start
bit
D0
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
D1
Figure 15-13. UART Reception
D2
D3
D4
D5
D6
D7
Parity
bit
Stop
bit
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