UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 302

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(6) TMQ0 option register 0 (TQ0OPT0)
The TQ0OPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
TQ0OPT0
After reset: 00H
Cautions 1. Rewrite the TQ0CCS3 to TQ0CCS0 bits when the
Remark
TQ0CCSm
TQ0CCS3
The TQ0CCSm bit setting is valid only in the free-running timer mode.
Set (1)
Reset (0)
• The TQ0OVF bit is set when the 16-bit counter count value overflows from
• An interrupt request signal (INTTQ0OV) is generated at the same time that the
• The TQ0OVF bit is not cleared even when the TQ0OVF bit or the TQ0OPT0
• The TQ0OVF bit can be both read and written, but the TQ0OVF bit cannot be set
FFFFH to 0000H in the free-running timer mode or the pulse width measurement
mode.
TQ0OVF bit is set to 1. The INTTQ0OV signal is not generated in modes other
than the free-running timer mode and the pulse width measurement mode.
register are read when the TQ0OVF bit = 1.
to 1 by software. Writing 1 has no influence on the operation of TMQ0.
0
1
7
TQ0OVF
TQ0CCS2 TQ0CCS1 TQ0CCS0
m = 0 to 3
Compare register selected
Capture register selected
R/W
2. Be sure to clear bits 1 to 3 to “0”.
6
TQ0CTL0.TQ0CE bit = 0. (The same value can be written
when the TQ0CE bit = 1.)
performed, clear the TQ0CE bit to 0 and then set the bits
again.
Address:
Overflow occurred
TQ0OVF bit 0 written or TQ0CTL0.TQ0CE bit = 0
TQ0CCRm register capture/compare selection
5
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
FFFFF545H
TMQ0 overflow detection
4
3
0
If rewriting was mistakenly
2
0
1
0
TQ0OVF
<0>
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