UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 653

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Maskable
Type
Classification Default
Interrupt
Priority
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
INTTP4OV
INTTP4CC0
INTTP4CC1
INTTP5OV
INTTP5CC0
INTTP5CC1
INTTM0EQ0 TMM0 compare match
INTCB0R/
INTIIC1
INTCB0T
INTCB1R
INTCB1T
INTCB2R
INTCB2T
INTCB3R
INTCB3T
INTUA0R/
INTCB4R
INTUA0T/
INTCB4T
INTUA1R/
INTIIC2
INTUA1T
INTUA2R/
INTIIC0
INTUA2T
INTAD
INTDMA0
INTDMA1
INTDMA2
INTDMA3
INTKR
INTWTI
INTWT
Name
TMP4 overflow
TMP4 capture 0/compare 0 match TMP4
TMP4 capture 1/compare 1 match TMP4
TMP5 overflow
TMP5 capture 0/compare 0 match TMP5
TMP5 capture 1/compare 1 match TMP5
CSIB0 reception completion/
CSIB0 reception error/
IIC1 transfer completion
CSIB0 consecutive transmission
write enable
CSIB1 reception completion/
CSIB1 reception error
CSIB1 consecutive transmission
write enable
CSIB2 reception completion/
CSIB2 reception error
CSIB2 consecutive transmission
write enable
CSIB3 reception completion/
CSIB3 reception error
CSIB3 consecutive transmission
write enable
UARTA0 reception completion/
CSIB4 reception completion/
CSIB4 reception error
UARTA0 consecutive transmission
enable/
CSIB4 consecutive transmission
write enable
UARTA1 reception completion/
UARTA1 reception error/
IIC2 transfer completion
UARTA1 consecutive transmission
enable
UARTA2 reception completion/
IIC0 transfer completion
UARTA2 consecutive transmission
enable
A/D conversion completion
DMA0 transfer completion
DMA1 transfer completion
DMA2 transfer completion
DMA3 transfer completion
Key return interrupt
Watch timer interval
Watch timer reference time
Table 19-1. Interrupt Source List (2/2)
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Trigger
Generating
TMP4
TMP5
TMM0
CSIB0/
IIC1
CSIB0
CSIB1
CSIB1
CSIB2
CSIB2
CSIB3
CSIB3
UARTA0/
CSIB4
UARTA0/
CSIB4
UARTA1/
IIC2
UARTA1
UARTA/
IIC0
UARTA2
A/D
DMA
DMA
DMA
DMA
KR
WT
WT
Unit
Exception
0220H
0230H
0240H
0250H
0260H
0270H
0280H
0290H
02A0H
02B0H
02C0H
02D0H
02E0H
02F0H
0300H
0310H
0320H
0330H
0340H
0350H
0360H
0370H
0380H
0390H
03A0H
03B0H
03C0H
03D0H
03E0H
Code
00000220H
00000230H
00000240H
00000250H
00000260H
00000270H
00000280H
00000290H
000002A0H
000002B0H
000002C0H
000002D0H
000002E0H
000002F0H
00000300H
00000310H
00000320H
00000330H
00000340H
00000350H
00000360H
00000370H
00000380H
00000390H
000003A0H
000003B0H
000003C0H
000003D0H
000003E0H
Address
Handler
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
Restored
PC
Page 637 of 870
TP4OVIC
TP4CCIC0
TP4CCIC1
TP5OVIC
TP5CCIC0
TP5CCIC1
TM0EQIC0
CB0RIC/
IICIC1
CB0TIC
CB1RIC
CB1TIC
CB2RIC
CB2TIC
CB3RIC
CB3TIC
UA0RIC/
CB4RIC
UA0TIC/
CB4TIC
UA1RIC/
IICIC2
UA1TIC
UA2RIC/
IICIC0
UA2TIC
ADIC
DMAIC0
DMAIC1
DMAIC2
DMAIC3
KRIC
WTIIC
WTIC
Interrupt
Register
Control