UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 558

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
After reset: 00H
(n = 0 to 2)
IICCn
Notes 1. The IICSn register, IICFn.STCFn and IICFn.IICBSYn bits, and IICCLn.CLDn and IICCLn.DADn bits
Caution If the I
Remark
Be sure to set this bit to 1 when the SCL0n and SDA0n lines are high level.
Condition for clearing (IICEn bit = 0)
• Cleared by instruction
• After reset
The standby mode following exit from communications remains in effect until the following communication entry
conditions are met.
• After a stop condition is detected, restart is in master mode.
• An address match occurs or an extension code is received after the start condition.
Condition for clearing (LRELn bit = 0)
• Automatically cleared after execution
• After reset
Condition for clearing (WRELn bit = 0)
• Automatically cleared after execution
• After reset
WRELn
LRELn
IICEn
IICEn
<7>
0
1
0
1
0
1
2. This flag’s signal is invalid when the IICEn bit = 0.
Note 2
Note 2
SDA0n line is low level, the start condition is detected immediately. To avoid this, after
enabling the I
instruction.
are reset.
The LRELn and WRELn bits are 0 when read after the data has been set.
Operation stopped. IICSn register reset
Operation enabled.
R/W
LRELn
Wait state not canceled
Wait state canceled. This setting is automatically cleared after wait state is canceled.
Normal operation
This exits from the current communication operation and sets standby mode. This setting is
automatically cleared after being executed. Its uses include cases in which a locally irrelevant
extension code has been received.
The SCL0n and SDA0n lines are set to high impedance.
The STTn and SPTn bits and the MSTSn, EXCn, COIn, TRCn, ACKDn, and STDn bits of the IICSn
register are cleared.
<6>
2
Cn operation is enabled (IICEn bit = 1) when the SCL0n line is high level and the
WRELn
<5>
2
Cn operation, immediately set the LRELn bit to 1 with a bit manipulation
Address: IICC0 FFFFFD82H, IICC1 FFFFFD92H, IICC2 FFFFFDA2H
SPIEn
<4>
Specification of I
Wait state cancellation control
WTIMn
Exit from communications
Note 1
<3>
. Internal operation stopped.
2
Cn operation enable/disable
Condition for setting (IICEn bit = 1)
• Set by instruction
Condition for setting (LRELn bit = 1)
• Set by instruction
Condition for setting (WRELn bit = 1)
• Set by instruction
ACKEn
<2>
STTn
<1>
SPTn
<0>
CHAPTER 17 I
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C BUS
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