UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 181

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
5.7
that is executed for each space selected as the memory block in the multiplex address/data bus mode. In the separate bus
mode, one idle state (TI) can be inserted after the T2 state. By inserting an idle state, the data output float delay time of
the memory can be secured during read access (an idle state cannot be inserted during write access).
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
To facilitate interfacing with low-speed memories, one idle state (TI) can be inserted after the T3 state in the bus cycle
Whether the idle state is to be inserted can be programmed by using the BCC register.
An idle state is inserted for all the areas immediately after system reset.
(1) Bus cycle control register (BCC)
Idle State Insertion Function
The BCC register can be read or written in 16-bit units.
Reset sets this register to AAAAH.
Cautions 1. The internal ROM, internal RAM, and on-chip peripheral I/O areas are not subject to idle state
Caution Be sure to set bits 15, 13, 11, and 9 to “1”, and clear bits 14, 12, 10, 8, 6, 4, 2, and 0 to “0”.
2. Write to the BCC register after reset, and then do not change the set values. Also, do not
After reset:
BCC
insertion.
access an external memory area until the initial settings of the BCC register are complete.
Memory block 3
BC31
BCn1
15
AAAAH
1
0
1
7
Not inserted
Inserted
14
0
0
6
R/W
Memory block 2
Specifies insertion of idle state (n = 0 to 3)
BC21
13
1
5
Address:
FFFFF48AH
12
0
4
0
Memory block 1
BC11
11
1
3
CHAPTER 5 BUS CONTROL FUNCTION
10
0
2
0
Memory block 0
BC01
1
9
1
0
0
8
0
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