UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 872

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
I
DMA
function
(DMA
controller)
2
Function
C bus
When
communication
among other
devices are in
progress
Operation
enable
IICCn.STTn,
SPTn bits
Transmission
reservation
Master
operation in
single master
system
Master
operation in
multimaster
system
Slave wait
cancellation
Master wait
cancellation
DSA0 to DSA3
registers
Details of
Function
When the IICCn.IICEn bit of the V850ES/JG3 is set to 1 while communications
among other devices are in progress, the start condition may be detected
depending on the status of the communication line. Be sure to set the IICCn.IICEn
bit to 1 when the SCL0n and SDA0n lines are high level.
Determine the operation clock frequency by the IICCLn, IICXn, and OCKSm
registers before enabling the operation (IICCn.IICEn bit = 1). To change the
operation clock frequency, clear the IICCn.IICEn bit to 0 once.
After the IICCn.STTn and IICCn.SPTn bits have been set to 1, they must not be
re-set without being cleared to 0 first.
If transmission has been reserved, set the IICCN.SPIEn bit to 1 so that an
interrupt request is generated by the detection of a stop condition. After an
interrupt request has been generated, the wait state will be released by writing
communication data to I
generated by the detection of a stop condition, transmission will halt in the wait
state because an interrupt request was not generated. However, it is not
necessary to set the SPIEn bit to 1 for the software to detect the IICSn.MSTSn bit.
Release the I
specifications of the product in communication.
For example, when the EEPROM outputs a low level to the SDA0n pin, set the
SCL0n pin to the output port and output clock pulses from that output port until
when the SDA0n pin is constantly high level.
Confirm that the bus release status (IICCLn.CLDn bit = 1, IICCLn.DADn bit = 1)
has been maintained for a certain period (1 frame, for example). When the SDA0n
pin is constantly low level, determine whether to release the I
SDA0n pins = high level) by referring to the specifications of the product in
communication.
Conform the transmission and reception formats to the specifications of the
product in communication.
When using the V850ES/JG3 as the master in the multimaster system, read the
IICSn.MSTSn bit for each INTIICn interrupt occurrence to confirm the arbitration
result.
When using the V850ES/JG3 as the slave in the multimaster system, confirm the
status using the IICSn and IICFn registers for each INTIICn interrupt occurrence
to determine the next processing.
To cancel slave wait, write FFH to IICn or set WRELn.
To cancel master wait, write FFH to IICn or set WRELn.
Be sure to clear bits 14 to 10 of the DSAnH register to 0.
Set the DSAnH and DSAnL registers at the following timing when DMA transfer is
disabled (DCHCn.Enn bit = 0).
• Period from after reset to start of first DMA transfer
• Period from after channel initialization by DCHCn.INITn bit to start of DMA
• Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of
transfer
the next DMA transfer
2
C0n bus (SCL0n, SDA0n pins = high level) in conformity with the
2
Cn, then transferring will begin. If an interrupt is not
Cautions
APPENDIX E LIST OF CAUTIONS
2
C0n bus (SCL0n,
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