UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 255

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(2) Operation timing in one-shot pulse output mode
External trigger input
(only when software
INTTPnCC0 signal
INTTPnCC1 signal
(a) Note on rewriting TPnCCRm register
TPnCCR0 register
TPnCCR1 register
TOPn0 pin output
TOPn1 pin output
(TIPn0 pin input)
trigger is used)
To change the set value of the TPnCCRm register to a smaller value, stop counting once, and then change the
set value.
If the value of the TPnCCRm register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
16-bit counter
When the TPnCCR0 register is rewritten from D
> D
than D
and less than D
count value. The counter counts up to FFFFH and then counts up again from 0000H. When the count value
matches D
matches D
Therefore, the counter may output a pulse with a delay period or active period different from that of the one-
shot pulse that is originally expected.
Remark
TPnCE bit
01
FFFFH
and D
0000H
11
and less than D
n = 0 to 5
m = 0, 1
11
01
10
, the counter generates the INTTPnCC1 signal and asserts the TOPn1 pin. When the count value
, the counter generates the INTTPnCC0 signal, deasserts the TOPn1 pin, and stops counting.
> D
00
, each set value is reflected as soon as the register has been rewritten and compared with the
11
, if the TPnCCR1 register is rewritten when the count value of the 16-bit counter is greater
10
and if the TPnCCR0 register is rewritten when the count value is greater than D
Delay
(D
D
10
10
)
Active level width
(D
00
D
− D
00
10
CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
+ 1)
D
10
D
00
Delay
(D
00
D
10
to D
10
)
Active level width
(D
00
01
D
− D
and the TPnCCR1 register from D
00
10
+ 1)
D
Delay
(10000H + D
10
D
00
11
)
Active level width
(D
D
D
D
01
11
11
01
D
− D
01
10
11
to D
Page 239 of 870
+ 1)
11
where D
00
01