UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 774

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(5) Securement of communication serial interface
• On-chip debug mode register (OCDM)
• Serial interface registers
• Interrupt mask register
UARTA0, CSIB0, or CSIB3 is used for communication between MINICUBE2 and the target system. The settings
related to the serial interface modes are performed by the debug monitor program, but if the setting is changed by
the user program, a communication error may occur.
To prevent such a problem from occurring, communication serial interface must be secured in the user program.
[How to secure communication serial interface]
Do not set the registers related to CSIB0, CSIB3, or UARTA0 in the user program.
When CSIB0 is used, do not mask the transmit end interrupt (INTCB0R). When CSIB3 is used, do not mask the
transmit end interrupt (INTCB3R). When UARTA0 is used, do not mask the receive end interrupt (INTUA0R).
For the on-chip debug function using the UARTA0, CSIB0, or CSIB3, set the OCDM register functions to normal
mode. Be sure to set as follows.
• Input low level to the P05/INTP2/DRST pin.
• Set the OCDM0 bit as shown below.
(a) When CSIB0 is used
(b) When CSIB3 is used
(C) When UARTA0 is used
Remark ×: don’t care
<1> Clear the OCDM0 bit to 0.
<2> Fix the P05/INTP2/DRST pin input to low level until the processing of <1> is complete.
CB0RIC
CB3RIC
UA0RIC
×
×
7
×
7
7
0
6
6
0
6
0
×
×
5
×
5
5
4
×
4
×
4
×
3
×
3
×
3
×
CHAPTER 28 ON-CHIP DEBUG FUNCTION
2
×
2
×
2
×
1
1
×
1
×
×
0
0
0
×
×
×
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