UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 684

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(4) Noise elimination control register (NFC)
Remarks 1. Since sampling is performed three times, the reliably eliminated noise width is 2 sampling clocks.
Digital noise elimination can be selected for the INTP3 pin. The noise elimination settings are performed using the
NFC register.
When digital noise elimination is selected, the sampling clock for digital sampling can be selected from among
f
When digital noise elimination is selected, if the clock that performs sampling in the standby mode is stopped, then
the INTP3 interrupt request signal cannot be used for releasing the standby mode. When f
sampling clock, the INTP3 interrupt request signal can be used for releasing either the subclock operating mode or
the IDLE1/IDLE2/STOP/sub-IDLE mode.
This register can be read or written in 8-bit units.
Reset sets this register to 00H.
Caution After the sampling clock has been changed, it takes 3 sampling clocks to initialize the digital
XX
/64, f
2. In the case of noise with a width smaller than 2 sampling clocks, an interrupt request signal is
XX
/128, f
After reset: 00H
generated if noise synchronized with the sampling clock is input.
NFC
noise eliminator. Therefore, if an INTP3 valid edge is input within these 3 sampling clocks after
the sampling clock has been changed, an interrupt request signal may be generated. Therefore,
be careful about the following points when using the interrupt and DMA functions.
• When using the interrupt function, after the 3 sampling clocks have elapsed, enable interrupts
• When using the DMA function (started by INTP3), enable DMA after 3 sampling clocks have
after the interrupt request flag (PIC3.PIF3 bit) has been cleared.
elapsed.
XX
/256, f
NFEN
NFEN
NFC2
0
1
0
0
0
0
1
1
Other than above
XX
/512, f
Analog noise elimination (60 ns (TYP.))
Digital noise elimination
R/W
NFC1
0
0
0
1
1
0
0
XX
/1,024, and f
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Address: FFFFF318H
NFC0
0
1
0
1
0
1
0
Settings of INTP3 pin noise elimination
f
f
f
f
f
f
Setting prohibited
XT
XX
XX
XX
XX
XX
XT
/64
/128
/256
/512
/1,024
. Sampling is performed three times.
(subclock)
0
0
Digital sampling clock
NFC2
NFC1
NFC0
XT
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is used as the