UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 383

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(i) Operation to write 0 (without conflict with setting)
(ii) Operation to write 0 (conflict with setting)
(e) Clearing overflow flag
(TQ0OVF bit)
(TQ0OVF bit)
Overflow flag
Overflow flag
The overflow flag can be cleared to 0 by clearing the TQ0OVF bit to 0 with the CLR instruction and by writing 8-
bit data (bit 0 is 0) to the TQ0OPT0 register. To accurately detect an overflow, read the TQ0OVF bit when it is 1,
and then clear the overflow flag by using a bit manipulation instruction.
To clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the CLR
instruction. If 0 is written to the overflow flag without checking if the flag is 1, the set information of overflow
may be erased by writing 0 ((ii) in the above chart). Therefore, software may judge that no overflow has
occurred even when an overflow actually has occurred.
If execution of the CLR instruction conflicts with occurrence of an overflow when the overflow flag is cleared to
0 with the CLR instruction, the overflow flag remains set even after execution of the clear instruction.
0 write signal
0 write signal
set signal
set signal
Overflow
Overflow
L
CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
(iii) Operation to clear to 0 (without conflict with setting)
(iv) Operation to clear to 0 (conflict with setting)
access signal
(TQ0OVF bit)
access signal
(TQ0OVF bit)
Overflow flag
Overflow flag
0 write signal
0 write signal
set signal
set signal
Overflow
Overflow
Register
Register
L
H
Read
Read
Write
Write
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