UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 531

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
SIBn pin capture
INTCBnR signal
INTCBnT signal
(2) Operation timing
CBnTSF bit
SCKBn pin
SOBn pin
(1) Write 00H to the CBnCTL1 register, and select communication type 1, communication clock (f
(2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits.
(3) Write E3H to the CBnCTL0 register, and select the transmission/reception mode, MSB first, and
(4) The CBnSTR.CBnTSF bit is set to 1 by writing the transmit data to the CBnTX register, and
(5) When transmission/reception is started, output the serial clock to the SCKBn pin, output the transmit
(6) When transfer of the transmit data from the CBnTX register to the shift register is completed and
(7) To continue transmission/reception, write the transmit data to the CBnTX register again after the
(8) When one transmission/reception is completed, the reception completion interrupt request signal
(9) When a new transmit data is written to the CBnTX register before communication completion, the next
(10) Read the CBnRX register.
Remark
SIBn pin
timing
f
continuous transfer mode at the same time as enabling the operation of the communication clock
(f
transmission/reception is started.
data to the SOBn pin in synchronization with the serial clock, and capture the receive data of the SIBn
pin.
writing to the CBnTX register is enabled, the transmission enable interrupt request signal (INTCBnT) is
generated.
INTCBnT signal is generated.
(INTCBnR) is generated, and reading of the CBnRX register is enabled.
communication is started following communication completion.
XX
CCLK
/2, and master mode.
(1)
(2)
(3)
).
n = 0 to 4
(4)
(5)
Bit 7
Bit 7
(6)
Bit 6
Bit 6
Bit 5 Bit 4 Bit 3
Bit 5 Bit 4 Bit 3
(7)
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
Bit 2
Bit 2
Bit 1
Bit 1
(8) (9) (10) (11)
Bit 0
Bit 0 Bit 7
Bit 7
Bit 6
Bit 6
Bit 5 Bit 4 Bit 3
Bit 5 Bit 4 Bit 3
Bit 2
Bit 2
Bit 1
Bit 1
(12)
Bit 0
Bit 0
(13) (15)
Page 515 of 870
CCLK
) =
(1/2)