UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 638

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
18.5 Transfer Modes
request, transfer is performed again once. This operation continues until a terminal count occurs.
request always takes precedence.
generated in a transfer cycle, DMA transfer of the channel with the lower priority is executed after the bus is released to the
CPU (the new transfer request of the same channel is ignored in the transfer cycle).
18.6 Transfer Types
write cycle, the transfer destination address is output and writing is performed from the DMAC to the destination.
between the transfer source and destination for DMA transfer of two cycles, the operation is performed as follows.
same transfer size as the register size. For example, for DMA transfer to an 8-bit register, be sure to specify byte (8-bit)
transfer.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Single transfer is supported as the transfer mode.
In single transfer mode, the bus is released at each byte/halfword transfer. If there is a subsequent DMA transfer
When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the higher priority DMA
If a new transfer request of the same channel and a transfer request of another channel with a lower priority are
As a transfer type, the 2-cycle transfer is supported.
In two-cycle transfer, data transfer is performed in two cycles, a read cycle and a write cycle.
In the read cycle, the transfer source address is output and reading is performed from the source to the DMAC. In the
An idle cycle of one clock is always inserted between a read cycle and a write cycle. If the data bus width differs
<16-bit data transfer>
For DMA transfer executed to an on-chip peripheral I/O register (transfer source/destination), be sure to specify the
Remark
<1> Transfer from 32-bit bus → 16-bit bus
<2> Transfer from 16-/32-bit bus to 8-bit bus
<3> Transfer from 8-bit bus to 16-/32-bit bus
<4> Transfer between 16-bit bus and 32-bit bus
A read cycle (the higher 16 bits are in a high-impedance state) is generated, followed by generation of a write
cycle (16 bits).
A 16-bit read cycle is generated once, and then an 8-bit write cycle is generated twice.
An 8-bit read cycle is generated twice, and then a 16-bit write cycle is generated once.
A 16-bit read cycle is generated once, and then a 16-bit write cycle is generated once.
The bus width of each transfer target (transfer source/destination) is as follows.
• On-chip peripheral I/O: 16-bit bus width
• Internal RAM:
• External memory:
32-bit bus width
8-bit or 16-bit bus width
CHAPTER 18 DMA FUNCTION (DMA CONTROLLER)
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