UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 424

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(1) Successive approximation register (SAR)
(2) A/D conversion result register n (ADA0CRn), A/D conversion result register nH (ADA0CRnH)
(3) A/D converter mode register 0 (ADA0M0)
(4) A/D converter mode register 1 (ADA0M1)
(5) A/D converter mode register 2 (ADA0M2)
(6) A/D converter channel specification register (ADA0S)
(7) Power-fail compare mode register (ADA0PFM)
(8) Power-fail compare threshold value register (ADA0PFT)
(9) Controller
(10) Sample & hold circuit
(11) Voltage comparator
The SAR register compares the voltage value of the analog input signal with the output voltage (compare voltage)
value of the compare voltage generation DAC, and holds the comparison result starting from the most significant bit
(MSB).
When the comparison result has been held down to the least significant bit (LSB) (i.e., when A/D conversion is
complete), the contents of the SAR register are transferred to the ADA0CRn register.
The ADA0CRn register is a 16-bit register that stores the A/D conversion result. ADA0ARn consist of 12 registers
and the A/D conversion result is stored in the 10 higher bits of the AD0CRn register corresponding to analog input.
(The lower 6 bits are fixed to 0.)
This register specifies the operation mode and controls the conversion operation by the A/D converter.
This register sets the conversion time of the analog input signal to be converted.
This register sets the hardware trigger mode.
This register sets the input port that inputs the analog voltage to be converted.
This register sets the power-fail monitor mode.
The ADA0PFT register sets a threshold value that is compared with the value of A/D conversion result register nH
(ADA0CRnH). The 8-bit data set to the ADA0PFT register is compared with the higher 8 bits of the A/D conversion
result register (ADA0CRnH).
The controller compares the result of the A/D conversion (the value of the ADA0CRnH register) with the value of the
ADA0PFT register when A/D conversion is completed or when the power-fail detection function is used, and
generates the INTAD signal only when a specified comparison condition is satisfied.
Remark
The sample & hold circuit samples each of the analog input signals selected by the input circuit and sends the
sampled data to the voltage comparator. This circuit also holds the sampled analog input signal voltage during
A/D conversion.
The voltage comparator compares a voltage value that has been sampled and held with the output voltage value
of the compare voltage generation DAC.
n = 0 to 11
CHAPTER 13 A/D CONVERTER
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