UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 850

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
This appendix lists cautions described in this document.
“Classification (hard/soft)” in table is as follows.
Hard:
Soft:
Introduction
Pin
functions
CPU
functions
Function
Cautions for microcontroller internal/external hardware
Cautions for software such as register settings or programs
FLMD0
REGC
P05
DDO
KR0 to KR7
NMI
When power is
turned on
EIPC register,
EIPSW register,
FEPC register,
FEPSW register
EIPC, FEPC,
CTPC registers
Program space Because the 4 KB area of addresses 03FFF000H to 03FFFFFFH is an on-chip
On-chip
peripheral I/O
area
Internal RAM
area
Details of
Function
Connect these pins to V
Connect the REGC pin to V
Incorporates a pull-down resistor. It can be disconnected by clearing the
OCDM.OCDM0 bit to 0.
In the on-chip debug mode, high-level output is forcibly set.
Pull this pin up externally.
The NMI pin alternately functions as the P02 pin. It functions as the P02 pin
after reset. To enable the NMI pin, set the PMC0.PMC02 bit to 1. The initial
setting of the NMI pin is “No edge detected”. Select the NMI pin valid edge
using INTF0 and INTR0 registers.
When the power is turned on, the following pin may output an undefined level
temporarily, even during reset.
• P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO pin
Because only one set of these registers is available, the contents of these
registers must be saved by program if multiple interrupts are enabled.
Even if EIPC or FEPC, or bit 0 of CTPC is set to 1 by the LDSR instruction, bit 0
is ignored when execution is returned to the main routine by the RETI
instruction after interrupt servicing (this is because bit 0 of the PC is fixed to 0).
Set an even value to EIPC, FEPC, and CTPC (bit 0 = 0).
peripheral I/O area, instructions cannot be fetched from this area. Therefore, do
not execute an operation in which the result of a branch address calculation
affects this area.
When a register is accessed in word units, a word area is accessed twice in
halfword units in the order of lower area and higher area, with the lower 2 bits of
the address ignored.
If a register that can be accessed in byte units is accessed in halfword units, the
higher 8 bits are undefined when the register is read, and data is written to the
lower 8 bits.
Addresses not defined as registers are reserved for future expansion. The
operation is undefined and not guaranteed when these addresses are
accessed.
If a branch instruction is at the upper limit of the internal RAM area, a prefetch
operation (invalid fetch) straddling the on-chip peripheral I/O area does not
occur.
APPENDIX E LIST OF CAUTIONS
SS
in the normal mode.
SS
via a 4.7
Cautions
μ
F (recommended value) capacitor.
APPENDIX E LIST OF CAUTIONS
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