UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 298

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(2) TMQ0 control register 1 (TQ0CTL1)
The TQ0CTL1 register is an 8-bit register that controls the operation of TMQ0.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
TQ0CTL1
After reset: 00H
Cautions 1. The TQ0EST bit is valid only in the external trigger pulse output
TQ0EEE
TQ0EST
The TQ0EEE bit selects whether counting is performed with the internal count clock
or the valid edge of the external event count input.
TQ0MD2
0
1
0
1
7
0
0
0
0
0
1
1
1
1
Generate a valid signal for external trigger input.
• In one-shot pulse output mode: A one-shot pulse is output with writing
• In external trigger pulse output mode: A PWM waveform is output with
Disable operation with external event count input.
(Perform counting with the count clock selected by the TQ0CTL0.TQ0CK0
to TQ0CK2 bits.)
Enable operation with external event count input.
(Perform counting at the valid edge of the external event count input
signal.)
TQ0EST TQ0EEE
TQ0MD1
R/W
2. External event count input is selected in the external event count
3. Set the TQ0EEE and TQ0MD2 to TQ0MD0 bits when the
4. Be sure to clear bits 3, 4, and 7 to “0”.
<6>
0
0
1
1
0
0
1
1
mode or one-shot pulse output mode. In any other mode, writing 1
to this bit is ignored.
mode regardless of the value of the TQ0EEE bit.
TQ0CTL0.TQ0CE bit = 0. (The same value can be written when the
TQ0CE bit = 1.) The operation is not guaranteed when rewriting is
performed with the TQ0CE bit = 1.
performed, clear the TQ0CE bit to 0 and then set the bits again.
Address:
TQ0MD0
<5>
0
1
0
1
0
1
0
1
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
FFFFF541H
Interval timer mode
External event count mode
External trigger pulse output mode
One-shot pulse output mode
PWM output mode
Free-running timer mode
Pulse width measurement mode
Setting prohibited
4
0
Software trigger control
Count clock selection
1 to the TQ0EST bit as the trigger.
3
0
−
Timer mode selection
writing 1 to the TQ0EST bit as
the trigger.
TQ0MD2 TQ0MD1 TQ0MD0
2
If rewriting was mistakenly
1
0
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