UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 867

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
D/A
converter
Asynchro-
nous serial
interface A
(UARTA)
Function
D/A converter
DA0M register
DA0CS0,
DA0CS1
registers
Cautions
CSIB4 and
UARTA0 mode
switching
UARTA2 and
I
switching
UARTA1 and
I
switching
UAnOPT0
register
SBF reception
Continuous
transmission
UART
reception
2
2
C00 mode
C02 mode
Details of
Function
DAC0 and DAC1 share the AV
DAC0 and DAC1 share the AV
converter.
The output trigger in the real-time output mode (DA0MDn bit = 1) is as follows.
• When n = 0: INTTP2CC0 signal (see CHAPTER 7 16-BIT TIMER/EVENT
• When n = 1: INTTP3CC0 signal (see CHAPTER 7 16-BIT TIMER/EVENT
In the real-time output mode (DA0M.DA0MDn bit = 1), set the DA0CSn register
before the INTTP2CC0/INTTP3CC0 signals are generated. D/A conversion starts
when the INTTP2CC0/INTTP3CC0 signals are generated.
Do not change the set value of the DA0CSn register while the trigger signal is
being issued in the real-time output mode.
Before changing the operation mode, be sure to clear the DA0M.DA0CEn bit to 0. p. 446
When using one of the P10/AN00 and P11/AN01 pins as an I/O port and the other
as a D/A output pin, do so in an application where the port I/O level does not
change during D/A output.
Make sure that AV
operation is not guaranteed.
Apply power to AV
No current can be output from the ANOn pin (n = 0, 1) because the output
impedance of the D/A converter is high. When connecting a resistor of 2 MΩ or
less, insert a JFET input operational amplifier between the resistor and the ANOn
pin.
Because the D/A converter stops operation in the STOP mode, the ANO0 and
ANO1 pins go into a highimpedance state, and the power consumption can be
reduced.
In the IDLE1, IDLE2, or subclock operation mode, however, the operation
continues. To lower the power consumption, therefore, clear the DA0M.DA0CEn
bit to 0.
The transmit/receive operation of CSIB4 and UARTA0 is not guaranteed if these
functions are switched during transmission or reception. Be sure to disable the
one that is not used.
The transmit/receive operation of UARTA2 and I
functions are switched during transmission or reception. Be sure to disable the
one that is not used.
The transmit/receive operation of UARTA1 and I
functions are switched during transmission or reception. Be sure to disable the
one that is not used.
Do not set the UAnSRT and UAnSTT bits (to 1) during SBF reception (UAnSRF
bit = 1).
If SBF is transmitted during a data reception, a framing error occurs.
Do not set the SBF reception trigger bit (UAnSRT) and SBF transmission trigger
bit (UAnSTT) to 1 during an SBF reception (UAnSRF = 1).
When initializing transmissions during the execution of continuous transmissions,
make sure that the UAnSTR.UAnTSF bit is 0, then perform the initialization.
Transmit data that is initialized when the UAnTSF bit is 1 cannot be guaranteed.
Be sure to read the UAnRX register even when a reception error occurs. If the
UAnRX register is not read, an overrun error occurs during reception of the next
data, and reception errors continue occurring indefinitely.
COUNTER P (TMP))
COUNTER P (TMP))
REF0
REF1
= V
at the same timing as AV
DD
= AV
REF1
SS
pin. The AV
REF1
pin.
Cautions
= 3.0 to 3.6 V. If this range is exceeded, the
SS
pin is also shared by the A/D
REF0
2
2
C00 is not guaranteed if these
C02 is not guaranteed if these
APPENDIX E LIST OF CAUTIONS
.
Page 851 of 870
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p. 442
p. 443
p. 444
p. 446
p. 446
p. 446
p. 446
p. 446
p. 446
p. 447
p. 448
p. 449
p. 455
p. 465
p. 465
p. 466
p. 470
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