UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 161

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(b) Cautions on alternate-function mode (input)
The input signal to the alternate-function block is low level when the PMCn.PMCnm bit is 0 due to the AND
output of the PMCn register set value and the pin level. Thus, depending on the port setting and alternate-
function operation enable timing, unexpected operations may occur. Therefore, switch between the port mode
and alternate-function mode in the following sequence.
• To switch from port mode to alternate-function mode (input)
• To switch from alternate-function mode (input) to port mode
The concrete examples are shown as Example 1 and Example 2.
[Example 1] Switch from general-purpose port (P02) to external interrupt pin (NMI)
Set the pins to the alternate-function mode using the PMCn register and then enable the alternate-function
operation.
Stop the alternate-function operation and then switch the pins to the port mode.
The order of setting in which malfunction may occur on switching from the P41 pin to the SCL01 pin
are shown below.
In <2>, I
pin. In the CMOS output period of <2> or <3>, unnecessary current may be generated.
<1>
<2>
<3>
<4>
Setting Order
When the P02/NMI pin is pulled up as shown in Figure 4-33 and the rising edge is specified in
the NMI pin edge detection setting, even though high level is input continuously to the NMI pin
during switching from the P02 pin to the an NMI pin (PMC02 bit = 0 → 1), this is detected as a
rising edge as if the low level changed to high level, and an NMI interrupt occurs.
To avoid it, set the NMI pin’s valid edge after switching from the P02 pin to the NMI pin.
2
C communication may be affected since the alternate-function SOB0 output is output to the
Initial value
(PMC41 bit = 0,
PFC41 bit = 0,
PF41 bit = 0)
PMC41 bit ← 1
PFC41 bit ← 1
PF41 bit ← 1
Setting Contents
Port mode (input)
SOB0 output
SCL01 I/O
SCL01 I/O
Pin States
Hi-Z
Low level (high level depending on the
CSIB0 setting)
High level (CMOS output)
Hi-Z (N-ch open-drain output)
CHAPTRER 4 PORT FUNCTIONS
Pin Level
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