UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 284

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
detected, the count value of the 16-bit counter is stored in the TPnCCRm register, the 16-bit counter is cleared to 0000H,
and a capture interrupt request signal (INTTPnCCm) is generated.
request signal (INTTPnOV) is generated at the next count clock, and the counter is cleared to 0000H and continues
counting. At this time, the overflow flag (TPnOPT0.TPnOVF bit) is also set to 1. Clear the overflow flag to 0 by executing
the CLR instruction via software.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
When the TPnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIPnm pin is later
The pulse width is calculated as follows.
If the valid edge is not input to the TIPnm pin even when the 16-bit counter counted up to FFFFH, an overflow interrupt
If the overflow flag is set to 1, the pulse width can be calculated as follows.
Remark
Pulse width = Captured value × Count clock cycle
Pulse width = (10000H × TPnOVF bit set (1) count + Captured value) × Count clock cycle
INTTPnCCm signal
Remark
TPnCCRm register
INTTPnOV signal
n = 0 to 5
m = 0, 1
TIPnm pin input
16-bit counter
TPnOVF bit
TPnCE bit
n = 0 to 5
m = 0, 1
FFFFH
0000H
Figure 7-35. Basic Timing in Pulse Width Measurement Mode
0000H
CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
D
0
D
1
Cleared to 0 by
CLR instruction
D
2
D
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