UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 645

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

DMA0 transfer request
DMA1 transfer request
DMA2 transfer request
<1> DMA0 transfer request
<2> New DMA0 transfer request is generated during DMA0 transfer.
<3> Requests for DMA0 and DMA1 are generated at the same time.
<4> Requests for DMA0, DMA1, and DMA2 are generated at the same time.
Mode of processing
System clock
DMA transfer
→ A DMA transfer request of the same channel is ignored during DMA transfer.
→ DMA0 request is ignored (a DMA transfer request of the same channel during transfer is ignored).
→ DMA1 request is acknowledged.
→ DMA1 request is ignored (a DMA transfer request of the same channel during transfer is ignored).
→ DMA0 request is acknowledged according to priority. DMA2 request is held pending (transfer of DMA2 occurs next).
DF1 bit
DF2 bit
DF0 bit
CPU processing
<1>
Preparation
for transfer
Figure 18-4. Period in Which DMA Transfer Request Is Ignored (2)
Read
DMA0 processing
<2>
Idle
Write
processing
End
CPU processing
<3>
Preparation
for transfer
Read
<4>
DMA1 processing
Idle
Write
processing
End
CPU processing
Preparation
for transfer
processing
Read
DMA0