UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 394

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
9.3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(1) TMM0 control register (TM0CTL0)
Register
The TM0CTL0 register is an 8-bit register that controls the TMM0 operation.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
The same value can always be written to the TM0CTL0 register by software.
TM0CTL0
After reset: 00H
Cautions 1. Set the TM0CKS2 to TM0CKS0 bits when TM0CE bit = 0.
Remark
TM0CKS2
The internal clock control and internal circuit reset for TMM0 are performed
asynchronously with the TM0CE bit. When the TM0CE bit is cleared to 0, the
internal clock of TMM0 is disabled (fixed to low level) and 16-bit counter is reset
asynchronously.
TM0CE
TM0CE
<7>
0
1
0
0
0
0
1
1
1
1
2. Be sure to clear bits 3 to 6 to “0”.
f
f
f
XX
R
XT
TM0CKS1
: Internal oscillation clock frequency
TMM0 operation disabled (16-bit counter reset asynchronously).
Operation clock application stopped.
TMM0 operation enabled. Operation clock application started. TMM0
operation started.
R/W
: Main clock frequency
: Subclock frequency
When changing the value of TM0CE from 0 to 1, it is not possible to set
the value of the TM0CKS2 to TM0CKS0 bits simultaneously.
6
0
0
0
1
1
0
0
1
1
Address: FFFFF690H
TM0CKS0
Internal clock operation enable/disable specification
5
0
0
1
0
1
0
1
0
1
f
f
f
f
f
INTWT
f
f
XX
XX
XX
XX
XX
R
XT
/8
4
0
/2
/4
/64
/512
CHAPTER 9 16-BIT INTERVAL TIMER M (TMM)
3
0
Count clock selection
TM0CKS2 TM0CKS1 TM0CKS0
2
1
0
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