UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 346

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOQ0k pin. After the
one-shot pulse is output, the 16-bit counter is set to FFFFH, stops counting, and waits for a trigger. If a trigger is
generated again while the one-shot pulse is being output, it is ignored.
value matches the value of the CCR0 buffer register. The compare match interrupt request signal INTTQ0CCk is
generated when the count value of the 16-bit counter matches the value of the CCRk buffer register.
trigger.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
TQ0CTL1
TQ0CTL0
When the TQ0CE bit is set to 1, 16-bit timer/event counter Q waits for a trigger. When the trigger is generated, the 16-
The output delay period and active level width of the one-shot pulse can be calculated as follows.
The compare match interrupt request signal INTTQ0CC0 is generated when the 16-bit counter counts after its count
The valid edge of an external trigger input or setting the software trigger (TQ0CTL1.TQ0EST bit) to 1 is used as the
Remark
Output delay period = (Set value of TQ0CCRk register) × Count clock cycle
Active level width = (Set value of TQ0CCR0 register − Set value of TQ0CCRk register + 1) × Count clock cycle
(a) TMQ0 control register 0 (TQ0CTL0)
(b) TMQ0 control register 1 (TQ0CTL1)
k = 1 to 3
TQ0CE
0/1
0
Figure 8-22. Register Setting for Operation in One-Shot Pulse Output Mode (1/3)
TQ0EST
0/1
0
TQ0EEE
0
0
0
0
CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
0
0
TQ0CKS2 TQ0CKS1 TQ0CKS0
TQ0MD2 TQ0MD1 TQ0MD0
0/1
0
0/1
1
0/1
1
0, 1, 1:
One-shot pulse output mode
Generate software trigger
when 1 is written
Select count clock
0: Stop counting
1: Enable counting
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