UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 213

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(6) TMPn option register 0 (TPnOPT0)
The TPnOPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
(n = 0 to 5)
TPnOPT0
After reset: 00H
Cautions 1. Rewrite the TPnCCS1 and TPnCCS0 bits when the TPnCE
TPnCCS1
TPnCCS0
Set (1)
Reset (0)
The TPnCCS1 bit setting is valid only in the free-running timer mode.
The TPnCCS0 bit setting is valid only in the free-running timer mode.
• The TPnOVF bit is set when the 16-bit counter count value overflows from
• An interrupt request signal (INTTPnOV) is generated at the same time that the
• The TPnOVF bit is not cleared even when the TPnOVF bit or the TPnOPT0
• The TPnOVF bit can be both read and written, but the TPnOVF bit cannot be set
FFFFH to 0000H in the free-running timer mode or the pulse width measurement
mode.
TPnOVF bit is set to 1. The INTTPnOV signal is not generated in modes other
than the free-running timer mode and the pulse width measurement mode.
register are read when the TPnOVF bit = 1.
to 1 by software. Writing 1 has no influence on the operation of TMPn.
0
1
0
1
0
7
TPnOVF
Compare register selected
Capture register selected
Compare register selected
Capture register selected
2. Be sure to clear bits 1 to 3, 6, and 7 to “0”.
R/W
bit = 0. (The same value can be written when the TPnCE
bit = 1.) If rewriting was mistakenly performed, clear the
TPnCE bit to 0 and then set the bits again.
6
0
Address:
TPnCCS1 TPnCCS0
Overflow occurred
TPnOVF bit 0 written or TPnCTL0.TPnCE bit = 0
TPnCCR1 register capture/compare selection
TPnCCR0 register capture/compare selection
5
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
TMPn overflow detection flag
TP0OPT0 FFFFF595H, TP1OPT0 FFFFF5A5H,
TP2OPT0 FFFFF5B5H, TP3OPT0 FFFFF5C5H,
TP4OPT0 FFFFF5D5H, TP5OPT0 FFFFF5E5H
4
3
0
2
0
1
0
TPnOVF
<0>
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