UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 634

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(5) DMA channel control registers 0 to 3 (DCHC0 to DCHC3)
Notes 1. The TCn bit is read-only.
Cautions 1. Be sure to clear bits 6 to 3 of the DCHCn register to 0.
The DCHC0 to DCHC3 registers are 8-bit registers that control the DMA transfer operating mode for DMA channel
n.
These registers can be read or written in 8-bit or 1-bit units. (However, bit 7 is read-only and bits 1 and 2 are write-
only. If bit 1 or 2 is read, the read value is always 0.)
Reset sets these registers to 00H.
2. The INITn and STGn bits are write-only.
2. When DMA transfer is completed (when a terminal count is generated), the Enn bit is
(n = 0 to 3)
cleared to 0 and then the TCn bit is set to 1. If the DCHCn register is read while its bits are
being updated, a value indicating “transfer not completed and transfer is disabled” (TCn bit
= 0 and Enn bit = 0) may be read.
DCHCn
After reset:
STGn
INITn
TCn
TCn
It is set to 1 on the last DMA transfer and cleared to 0 when it is read.
DMA transfer is enabled when the Enn bit is set to 1.
When DMA transfer is completed (when a terminal count is generated), this bit is
automatically cleared to 0.
To abort DMA transfer, clear the Enn bit to 0 by software. To resume, set the Enn
bit to 1 again.
When aborting or resuming DMA transfer, however, be sure to observe the
procedure described in 18.13 Cautions.
00H
Enn
<7>
0
1
0
1
Note 1
Note 1
Note 2
Note 2
DMA transfer had not completed.
DMA transfer had completed.
If the INITn bit is set to 1 with DMA transfer disabled (Enn bit = 0), the
DMA transfer status can be initialized.
When re-setting the DMA transfer status (re-setting the DDAnH, DDAnL,
DSAnH, DSAnL, DBCn, and DADCn registers) before DMA transfer is
completed (before the TCn bit is set to 1), be sure to initialize the DMA
channel.
When initializing the DMA controller, however, be sure to observe the
procedure described in 18.13 Cautions.
This is a software startup trigger of DMA transfer.
If this bit is set to 1 in the DMA transfer enable state (TCn bit = 0, Enn
bit = 1), DMA transfer is started.
DMA transfer disabled
DMA transfer enabled
R/W
0
6
Address:
through DMA channel n has completed or not
5
0
DMA channel n is to be enabled or disabled
Status flag indicates whether DMA transfer
Setting of whether DMA transfer through
CHAPTER 18 DMA FUNCTION (DMA CONTROLLER)
DCHC0 FFFFF0E0H, DCHC1 FFFFF0E2H,
DCHC2 FFFFF0E4H, DCHC3 FFFFF0E6H
4
0
3
0
INITn
<2>
Note 2
STGn
<1>
Note 2
Enn
<0>
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