UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 469

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
15.4 Registers
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(1) UARTAn control register 0 (UAnCTL0)
The UAnCTL0 register is an 8-bit register that controls the UARTAn serial transfer operation.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 10H.
(n = 0 to 2)
UAnCTL0
After reset: 10H
UAnPWR
UAnPWR
UAnRXE
The UARTAn operation is controlled by the UAnPWR bit. The TXDAn pin output
is fixed to high level by clearing the UAnPWR bit to 0 (fixed to low level if
UAnOPT0.UAnTDL bit = 1).
UAnTXE
• To start transmission, set the UAnPWR bit to 1 and then set the UAnTXE bit to 1.
• To initialize the transmission unit, clear the UAnTXE bit to 0, wait for two cycles of
• To start reception, set the UAnPWR bit to 1 and then set the UAnRXE bit to 1.
• To initialize the reception unit, clear the UAnRXE bit to 0, wait for two periods of
To stop, transmission clear the UAnTXE bit to 0 and then UAnPWR bit to 0.
the base clock, and then set the UAnTXE bit to 1 again. Otherwise, initialization
may not be executed (for the base clock, see 15.7 (1) (a) Base clock).
To stop reception, clear the UAnRXE bit to 0 and then UAnPWR bit to 0.
the base clock, and then set the UAnRXE bit to 1 again. Otherwise, initialization
may not be executed (for the base clock, see 15.7 (1) (a) Base clock).
<7>
0
1
0
1
0
1
Disable UARTAn operation (UARTAn reset asynchronously)
Enable UARTAn operation
Disable transmission operation
Enable transmission operation
Disable reception operation
Enable reception operation
R/W
UAnTXE UAnRXE UAnDIR
<6>
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
Address: UA0CTL0 FFFFFA00H, UA1CTL0 FFFFFA10H,
<5>
UA2CTL0 FFFFFA20H
Transmission operation enable
Reception operation enable
UARTAn operation control
<4>
UAnPS1 UAnPS0
3
2
UAnCL
1
UAnSL
0
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