UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 868

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Asynchro-
nous serial
interface A
(UARTA)
Function
UART
reception
Reception
errors
LIN function
UAnCTL1
register
UAnCTL2
register
Baud rate error
Allowable baud
rate range
during
reception
When the clock
supply to
UARTAn is
stopped
RXDA1 pin
KR7 pin
Performing the
transfer of
transmit data
and receive
data using
DMA transfer
Details of
Function
The operation during reception is performed assuming that there is only one stop
bit. A second stop bit is ignored.
When reception is completed, read the UAnRX register after the reception
complete interrupt request signal (INTUAnR) has been generated, and clear the
UAnPWR or UAnRXE bit to 0. If the UAnPWR or UAnRXE bit is cleared to 0
before the INTUAnR signal is generated, the read value of the UAnRX register
cannot be guaranteed.
If receive completion processing (INTUAnR signal generation) of UARTAn and
the UAnPWR bit = 0 or UAnRXE bit = 0 conflict, the INTUAnR signal may be
generated in spite of these being no data stored in the UAnRX register.
To complete reception without waiting INTUAnR signal generation, be sure to
clear (0) the interrupt request flag (UAnRIF) of the UAnRIC register, after setting
(1) the interrupt mask flag (UAnRMK) of the interrupt control register (UAnRIC)
and then set (1) the UAnPWR bit = 0 or UAnRXE bit = 0.
When an INTUAnR signal is generated, the UAnSTR register must be read to
check for errors.
If a receive error interrupt occurs during continuous reception, read the contents
of the UAnSTR register must be read before the next reception is completed, then
perform error processing.
When using the LIN function, fix the UAnPS1 and UAnPS0 bits of the UAnCTL0
register to 00.
Clear the UAnCTL0.UAnPWR bit to 0 before rewriting the UAnCTL1 register.
Clear the UAnCTL0.UAnPWR bit to 0 or clear the UAnTXE and UAnRXE bits to
00 before rewriting the UAnCTL2 register.
The baud rate error during transmission must be within the error tolerance on the
receiving side.
The baud rate error during reception must satisfy the range indicated in (5)
Allowable baud rate range during reception.
The baud rate error during reception must be set within the allowable error range
using the following equation.
When the clock supply to UARTAn is stopped (for example, in IDLE1, IDLE2, or
STOP mode), the operation stops with each register retaining the value it had
immediately before the clock supply was stopped. The TXDAn pin output also
holds and outputs the value it had immediately before the clock supply was
stopped. However, the operation is not guaranteed after the clock supply is
resumed. Therefore, after the clock supply is resumed, the circuits should be
initialized by setting the UAnCTL0.UAnPWR, UAnCTL0.UAnRXEn, and
UAnCTL0.UAnTXEn bits to 000.
The RXDA1 and KR7 pins must not be used at the same time. To use the RXDA1
pin, do not use the KR7 pin. To use the KR7 pin, do not use the RXDA1 pin (it is
recommended to set the PFC91 bit to 1 and clear PFCE91 bit to 0).
In UARTAn, the interrupt caused by a communication error does not occur. When
performing the transfer of transmit data and receive data using DMA transfer,
error processing cannot be performed even if errors (parity, overrun, framing)
occur during transfer. Either read the UAnSTR register after DMA transfer has
been completed to make sure that there are no errors, or read the UAnSTR
register during communication to check for errors.
Cautions
APPENDIX E LIST OF CAUTIONS
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