UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 208

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(1) TMPn control register 0 (TPnCTL0)
(2) TMPn control register 1 (TPnCTL1)
The TPnCTL0 register is an 8-bit register that controls the operation of TMPn.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
The same value can always be written to the TPnCTL0 register by software.
The TPnCTL1 register is an 8-bit register that controls the operation of TMPn.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
(n = 0 to 5)
TPnCTL0
After reset: 00H
Note TPn0PT0.TPnOVF bit, 16-bit counter, timer output (TOPn0, TOPn1 pins)
Cautions 1. Set the TPnCKS2 to TPnCKS0 bits when the TPnCE bit = 0.
Remark
TPnCKS2
TPnCE
TPnCE
<7>
0
1
0
0
0
0
1
1
1
1
TMPn operation disabled (TMPn reset asynchronously
TMPn operation enabled. TMPn operation started.
TPnCKS1
f
R/W
2. Be sure to clear bits 3 to 6 to “0”.
XX
: Main clock frequency
6
0
When the value of the TPnCE bit is changed from 0 to 1, the
TPnCKS2 to TPnCKS0 bits can be set simultaneously.
0
0
1
1
0
0
1
1
Address:
TPnCKS0
5
0
0
1
0
1
0
1
0
1
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
TP0CTL0 FFFFF590H, TP1CTL0 FFFFF5A0H,
TP2CTL0 FFFFF5B0H, TP3CTL0 FFFFF5C0H,
TP4CTL0 FFFFF5D0H, TP5CTL0 FFFFF5E0H
f
f
f
f
f
f
f
f
XX
XX
XX
XX
XX
XX
XX
XX
TMPn operation control
4
0
/2
/4
/8
/16
/32
/64
/128
n = 0, 2, 4
Internal count clock selection
3
0
TPnCKS2 TPnCKS1 TPnCKS0
2
f
f
XX
XX
/256
/512
Note
n = 1, 3, 5
).
1
0
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