UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 232

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(e) TMPn counter read buffer register (TPnCNT)
(f) TMPn capture/compare register 0 (TPnCCR0)
(g) TMPn capture/compare register 1 (TPnCCR1)
The count value of the 16-bit counter can be read by reading the TPnCNT register.
If D
(INTTPnCC0) is generated when the number of external event counts reaches (D
Usually, the TPnCCR1 register is not used in the external event count mode. However, the set value of the
TPnCCR1 register is transferred to the CCR1 buffer register. When the count value of the 16-bit counter
matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTPnCC1) is
generated.
Therefore, mask the interrupt signal by using the interrupt mask flag (TPnCCMK1).
Caution When an external clock is used as the count clock, the external clock can be input only
Remarks 1. TMPn I/O control register 1 (TPnIOC1) and TMPn option register 0 (TPnOPT0) are not used
0
is set to the TPnCCR0 register, the counter is cleared and a compare match interrupt request signal
Figure 7-11. Register Setting for Operation in External Event Count Mode (2/2)
from the TIPn0 pin. At this time, set the TPnIOC1.TPnIS1 and TPnIOC1.TPnIS0 bits to 00
(capture trigger input (TIPn0 pin): no edge detection).
2. n = 0 to 5
in the external event count mode.
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
0
+ 1).
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