UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 179

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UPD70F3740GC-UEU-AX

Manufacturer Part Number
UPD70F3740GC-UEU-AX
Description
MCU 32BIT V850ES/JX3 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3r
Datasheet

Specifications of UPD70F3740GC-UEU-AX

Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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V850ES/JG3
5.6.3
programmable wait and the wait cycles controlled by the WAIT pin.
be inserted in the bus cycle.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Wait cycles are inserted as the result of an OR operation between the wait cycles specified by the set value of the
For example, if the timing of the programmable wait and the WAIT pin signal is as illustrated below, three wait states will
Remark
Relationship between programmable wait and external wait
Programmable wait
Programmable wait
Wait via WAIT pin
Wait via WAIT pin
The circles indicate the sampling timing.
Wait control
Wait control
WAIT pin
CLKOUT
WAIT pin
CLKOUT
Programmable wait
Wait via WAIT pin
T1
Figure 5-3. Inserting Wait Example
T1
(a) Multiplexed bus
T2
(b) Separate bus
TW
TW
TW
CHAPTER 5 BUS CONTROL FUNCTION
TW
TW
Wait control
TW
T2
T3
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