UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 564

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Remark
Condition for clearing (STDn bit = 0)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock
• Cleared by LRELn bit = 1 (communication save)
• When the IICEn bit changes from 1 to 0 (operation
• After reset
Condition for clearing (SPDn bit = 0)
• At the rising edge of the address transfer byte’s first
• When the IICEn bit changes from 1 to 0 (operation
• After reset
following address transfer
stop)
clock following setting of this bit and detection of a
start condition
stop)
STDn
SPDn
0
1
0
1
n = 0 to 2
Start condition was not detected.
Start condition was detected. This indicates that the address transfer period is in effect
Stop condition was not detected.
Stop condition was detected. The master device’s communication is terminated and the bus is
released.
Start condition detection
Stop condition detection
Condition for setting (STDn bit = 1)
• When a start condition is detected
Condition for setting (SPDn bit = 1)
• When a stop condition is detected
CHAPTER 17 I
Page 548 of 870
2
C BUS
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