UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 9

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 5 BUS CONTROL FUNCTION .......................................................................................... 149
CHAPTER 6 CLOCK GENERATION FUNCTION .............................................................................. 175
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) ................................................................ 188
4.4
4.5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
6.1
6.2
6.3
6.4
6.5
7.1
7.2
7.3
7.4
7.5
4.3.10
4.3.11
Block Diagrams..................................................................................................................... 106
Port Register Settings When Alternate Function Is Used ................................................ 136
Features................................................................................................................................. 149
Bus Control Pins................................................................................................................... 150
5.2.1
5.2.2
Memory Block Function....................................................................................................... 151
External Bus Interface Mode Control Function ................................................................. 152
Bus Access ........................................................................................................................... 153
5.5.1
5.5.2
5.5.3
Wait Function ........................................................................................................................ 161
5.6.1
5.6.2
5.6.3
5.6.4
Idle State Insertion Function ............................................................................................... 165
Bus Hold Function................................................................................................................ 166
5.8.1
5.8.2
5.8.3
Bus Priority ........................................................................................................................... 168
Bus Timing ............................................................................................................................ 169
Overview................................................................................................................................ 175
Configuration ........................................................................................................................ 176
Registers ............................................................................................................................... 178
Operation............................................................................................................................... 183
6.4.1
6.4.2
PLL Function......................................................................................................................... 184
6.5.1
6.5.2
6.5.3
Overview................................................................................................................................ 188
Functions............................................................................................................................... 188
Configuration ........................................................................................................................ 189
Registers ............................................................................................................................... 191
Operation............................................................................................................................... 203
7.5.1
7.5.2
7.5.3
Port DH ....................................................................................................................................101
Port DL.....................................................................................................................................103
Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed ...............150
Pin status in each operation mode...........................................................................................150
Number of clocks for access ....................................................................................................153
Bus size setting function ..........................................................................................................153
Access by bus size ..................................................................................................................154
Programmable wait function.....................................................................................................161
External wait function...............................................................................................................162
Relationship between programmable wait and external wait ...................................................163
Programmable address wait function.......................................................................................164
Functional outline.....................................................................................................................166
Bus hold procedure..................................................................................................................167
Operation in power save mode ................................................................................................167
Operation of each clock ...........................................................................................................183
Clock output function ...............................................................................................................183
Overview..................................................................................................................................184
Registers..................................................................................................................................184
Usage ......................................................................................................................................187
Interval timer mode (TPnMD2 to TPnMD0 bits = 000) .............................................................204
External event count mode (TPnMD2 to TPnMD0 bits = 001) .................................................214
External trigger pulse output mode (TPnMD2 to TPnMD0 bits = 010) .....................................222