UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 193

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(1) Main clock oscillator
(2) Subclock oscillator
(3) Main clock oscillator stop control
(4) Internal oscillator
(5) Prescaler 1
(6) Prescaler 2
(7) Prescaler 3
(8) PLL
The main resonator oscillates the following frequencies (f
• In clock-through mode
• In PLL mode
The sub-resonator oscillates a frequency of 32.768 kHz (f
This circuit generates a control signal that stops oscillation of the main clock oscillator.
Oscillation of the main clock oscillator is stopped in the STOP mode or when the PCC.MCK bit = 1 (valid only when
the PCC.CLS bit = 1).
Oscillates a frequency (f
This prescaler generates the clock (f
TMP0 to TMP5, TMQ0, TMM0, CSIB0 to CSIB4, UARTA0 to UARTA2, I
This circuit divides the main clock (f
The clock generated by prescaler 2 (f
and internal system clock (f
f
This circuit divides the clock generated by the main clock oscillator (f
supplies that clock to the watch timer block.
For details, see CHAPTER 10 WATCH TIMER FUNCTIONS.
This circuit multiplies the clock generated by the main clock oscillator (f
It operates in two modes: clock-through mode in which f
is output. These modes can be selected by using the PLLCTL.SELPLL bit.
Whether the clock is multiplied by 4 or 8 is selected by the CKC.CKDIV0 bit, and PLL is started or stopped by the
PLLCTL.PLLON bit.
CLK
f
f
f
X
X
X
is the clock supplied to the INTC, ROM, and RAM blocks, and can be output from the CLKOUT pin.
= 2.5 to 10 MHz
= 2.5 to 5 MHz (×4)
= 2.5 to 4 MHz (×8)
R
) of 220 kHz (TYP.).
CLK
).
XX
).
XX
XX
to f
to f
XX
XX
/1,024) to be supplied to the following on-chip peripheral functions:
/32) is supplied to the selector that generates the CPU clock (f
X
X
XT
CHAPTER 6 CLOCK GENERATION FUNCTION
).
is output as is, and PLL mode in which a multiplied clock
).
X
X
) to a specific frequency (32.768 kHz) and
) by 4 or 8.
2
C00 to I
2
C02, ADC, and WDT2
Page 177 of 870
CPU
)