UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 775

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
• Port registers when UARTA0 is used
• Port registers when CSIB0 is used
When UARTA0 is used, port registers are set to make the TXDA0 and RXDA0 pins valid by the debug monitor
program. Do not change the following register settings with the user program during debugging. (The same
value can be overwritten.)
When CSIB0 is used, port registers are set to make the SIB0, SOB0, SCKB0, and HS (PMC0) pins valid by the
debug monitor program. Do not change the following register settings with the user program during debugging.
(The same value can be overwritten.)
(a) SIB0, SOB0, and SCKB0 settings
(b) HS (PMC0 pin) settings
Remark ×: don’t care
Note Writing to this bit is prohibited.
Remark ×: don’t care
PMC3L
PFC3
PMCM
PMC4
PFC4
The port values corresponding to the HS pin are changed by the monitor program according to
the debugger status. To perform port register settings in 8-bit units, the user program can
usually use read-modify-write. If an interrupt for debugging occurs before writing, however, an
unexpected operation may be performed.
PCM
×
7
×
7
7
×
7
×
7
×
7
×
×
6
×
6
6
6
6
×
×
6
×
×
×
5
5
×
5
5
×
5
×
×
5
×
4
×
4
×
4
4
4
×
×
4
×
×
3
3
×
×
3
×
3
×
3
3
×
×
CHAPTER 28 ON-CHIP DEBUG FUNCTION
2
2
×
×
2
1
2
×
2
×
2
×
1
0
1
1
1
1
1
0
1
×
1
×
0
0
0
1
Note
0
0
1
0
0
0
0
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