UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 879

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Key
interrupt
function
Standby
function
Function
KRM register
KR0 to KR7
pins
RXDA1 pin
KR7 pin
Use the key
interrupt
function
PSC register
PSMR register
OSTS register
HALT mode
IDLE1 mode
Releasing
IDLE1 mode
IDLE2 mode
Details of
Function
Rewrite the KRM register after once clearing the KRM register to 00H.
If the KRM register is changed, an interrupt request signal (INTKR) may be
generated. To prevent this, change the KRM register after disabling interrupts (DI)
or masking, then clear the interrupt request flag (KRIC.KRIF bit) to 0, and enable
interrupts (EI) or clear the mask.
If a low level is input to any of the KR0 to KR7 pins, the INTKR signal is not
generated even if the falling edge of another pin is input.
The RXDA1 and KR7 pins must not be used at the same time. To use the RXDA1
pin, do not use the KR7 pin.
To use the KR7 pin, do not use the RXDA1 pin (it is recommended to set the
PFC91 bit to 1 and clear PFCE91 bit to 0).
To use the key interrupt function, be sure to set the port pin to the key return pin
and then enable the operation with the KRM register. To switch from the key
return pin to the port pin, disable the operation with the KRM register and then set
the port pin.
Before setting the IDLE1, IDLE2, STOP, or sub-IDLE mode, set the PSMR.PSM1
and PSMR.PSM0 bits and then set the STP bit.
Settings of the NMI1M, NMI0M, and INTM bits are invalid when HALT mode is
released.
If the NMI1M, NMI0M, or INTM bit is set to 1 at the same time the STP bit is set to
1, the setting of NMI1M, NMI0M, or INTM bit becomes invalid. If there is an
unmasked interrupt request signal being held pending when the
IDLE1/IDLE2/STOP mode is set, set the bit corresponding to the interrupt request
signal (NMI1M, NMI0M, or INTM) to 1, and then set the STP bit to 1.
Be sure to clear bits 2 to 7 to “0”.
The PSM0 and PSM1 bits are valid only when the PSC.STP bit is 1.
The wait time following release of the STOP mode does not include the time until
the clock oscillation starts (“a” in the figure below) following release of the STOP
mode, regardless of whether the STOP mode is released by reset or the
occurrence of an interrupt request signal.
Be sure to clear bits 3 to 7 to “0”.
The oscillation stabilization time following reset release is 2
value of the OSTS register = 06H).
Insert five or more NOP instructions after the HALT instruction.
If the HALT instruction is executed while an unmasked interrupt request signal is
being held pending, the status shifts to HALT mode, but the HALT mode is then
released immediately by the pending interrupt request.
Insert five or more NOP instructions after the instruction that stores data in the
PSC register to set the IDLE1 mode.
If the IDLE1 mode is set while an unmasked interrupt request signal is being held
pending, the IDLE1 mode is released immediately by the pending interrupt
request.
An interrupt request signal that is disabled by setting the PSC.NMI1M,
PSC.NMI0M, and PSC.INTM bits to 1 becomes invalid and IDLE1 mode is not
released.
Insert five or more NOP instructions after the instruction that stores data in the
PSC register to set the IDLE2 mode.
If the IDLE2 mode is set while an unmasked interrupt request signal is being held
pending, the IDLE2 mode is released immediately by the pending interrupt
request.
Cautions
APPENDIX E LIST OF CAUTIONS
16
/f
X
(because the initial
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