UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 577

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
17.6.4 ACK
receiving device, the reception is judged as normal and processing continues. The detection of ACK is confirmed with the
IICSn.ACKDn bit.
stop condition. When the slave device is the receiving device and does not return ACK, the master device generates
either a stop condition or a restart condition, and then stops the current transmission. Failure to return ACK may be
caused by the following factors.
the 7 address data bits causes the IICSn.TRCn bit to be set. Normally, set the ACKEn bit to 1 for reception (TRCn bit = 0).
receive any more data, clear the ACKEn bit to 0 to indicate to the master that no more data can be received.
ACKEn bit to 0 to prevent ACK from being generated. This notifies the slave device (transmitting device) of the end of the
data transmission (transmission stopped).
is generated if the received address is not a local address (NACK).
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
ACK is used to confirm the serial data status of the transmitting and receiving devices.
The receiving device returns ACK for every 8 bits of data it receives.
The transmitting device normally receives ACK after transmitting 8 bits of data. When ACK is returned from the
When the master device is the receiving device, after receiving the final data, it does not return ACK and generates the
(a) Reception was not performed normally.
(b) The final data was received.
(c) The receiving device (slave) does not exist for the specified address.
When the receiving device sets the SDA0n line to low level during the ninth clock, ACK is generated (normal reception).
When the IICCn.ACKEn bit is set to 1, automatic ACK generation is enabled. Transmission of the eighth bit following
When the slave device is receiving (when TRCn bit = 0), if the slave device cannot receive data or does not need to
Similarly, when the master device is receiving (when TRCn bit = 0) and the subsequent data is not needed, clear the
When the local address is received, ACK is automatically generated regardless of the value of the ACKEn bit. No ACK
When receiving the extension code, set the ACKEn bit to 1 in advance to generate ACK.
The ACK generation method during data reception is based on the wait timing setting, as described by the following.
• When 8-clock wait is selected (IICCn.WTIMn bit = 0):
• When 9-clock wait is selected (IICCn.WTIMn bit = 1):
Remark
Remark
ACK is generated at the falling edge of the SCL0n pin’s eighth clock if the ACKEn bit is set to 1 before the wait state
cancellation.
ACK is generated if the ACKEn bit is set to 1 in advance.
n = 0 to 2
n = 0 to 2
SDA0n
SCL0n
AD6
1
AD5
2
Figure 17-11. ACK
AD4
3
AD3
4
AD2
5
AD1
6
AD0
7
R/W ACK
8
9
CHAPTER 17 I
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C BUS