UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 258

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
PWM waveform from the TOPn1 pin.
written value is reflected when the count value of the 16-bit counter matches the value of the CCR0 buffer register and the
16-bit counter is cleared to 0000H.
count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare
match interrupt request signal INTTPnCC1 is generated when the count value of the 16-bit counter matches the value of
the CCR1 buffer register.
counter matches the value of the CCRm buffer register and the 16-bit counter is cleared to 0000H.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
When the TPnCE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
The PWM waveform can be changed by rewriting the TPnCCRm register while the counter is operating. The newly
The compare match interrupt request signal INTTPnCC0 is generated when the 16-bit counter counts next time after its
The value set to the TPnCCRm register is transferred to the CCRm buffer register when the count value of the 16-bit
Remark
Active level width = (Set value of TPnCCR1 register ) × Count clock cycle
Cycle = (Set value of TPnCCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TPnCCR1 register)/(Set value of TPnCCR0 register + 1)
CCR0 buffer register
CCR1 buffer register
n = 0 to 5, m = 0, 1
INTTPnCC0 signal
INTTPnCC1 signal
TPnCCR0 register
TPnCCR1 register
TOPn0 pin output
TOPn1 pin output
16-bit counter
TPnCE bit
FFFFH
0000H
Figure 7-25. Basic Timing in PWM Output Mode
Active period
D
(D
10
D
10
00
)
(D
D
D
Cycle
00
10
CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
D
00
D
D
10
10
D
+ 1)
00
00
D
Inactive period
(D
10
D
00
00
− D
10
+ 1)
D
D
11
01
D
01
D
D
D
D
11
11
01
11
D
01
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