UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 203

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
6.5.3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(4) PLL lockup time specification register (PLLS)
(1) When PLL is used
(2) When PLL is not used
Cautions 1. Set so that the lockup time is 800
The PLLS register is an 8-bit register used to select the PLL lockup time when the PLLCTL.PLLON bit is changed
from 0 to 1.
This register can be read or written in 8-bit units.
Reset sets this register to 03H.
• After the reset signal has been released, the PLL operates (PLLCTL.PLLON bit = 1), but because the default
• To enable PLL operation, first set the PLLON bit to 1, and then set the SELPLL bit to 1 after the LOCKR.LOCK
• The PLL stops during transition to the IDLE2 or STOP mode regardless of the setting and is restored from the
• The clock-through mode (SELPLL bit = 0) is selected after the reset signal has been released, but the PLL is
Usage
mode is the clock-through mode (PLLCTL.SELPLL bit = 0), select the PLL mode (SELPLL bit = 1).
bit = 0. To stop the PLL, first select the clock-through mode (SELPLL bit = 0), wait for 8 clocks or more, and then
stop the PLL (PLLON bit = 0).
IDLE2 or STOP mode to the status before transition. The time required for restoration is as follows.
When transiting to the IDLE1 mode, the PLL does not stop. Stop the PLL if necessary.
operating (PLLON bit = 1) and must therefore be stopped (PLLON bit = 0).
(a) When transiting to the IDLE2 or STOP mode from the clock through mode
(b) When transiting to the IDLE 2 or STOP mode while remaining in the PLL operation mode
• STOP mode: Set the OSTS register so that the oscillation stabilization time is 1 ms (min.) or longer.
• IDLE2 mode: Set the OSTS register so that the setup time is 350
• STOP mode: Set the OSTS register so that the oscillation stabilization time is 1 ms (min.) or longer.
• IDLE2 mode: Set the OSTS register so that the setup time is 800
2. Do not change the PLLS register setting during the lockup period.
PLLS
After reset: 03H
PLLS1
0
0
1
1
0
PLLS0
R/W
0
0
1
0
1
Address: FFFFF6C1H
2
2
2
2
10
11
12
13
0
/f
f
/f
/f
X
X
X
X
(default value)
μ
s or longer.
0
Selection of PLL lockup time
CHAPTER 6 CLOCK GENERATION FUNCTION
0
0
μ
μ
PLLS1
s (min.) or longer.
s (min.) or longer.
PLLS0
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