UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 609

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UPD70F3740GC-UEU-AX

Manufacturer Part Number
UPD70F3740GC-UEU-AX
Description
MCU 32BIT V850ES/JX3 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3r
Datasheet

Specifications of UPD70F3740GC-UEU-AX

Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Manufacturer
Quantity
Price
Part Number:
UPD70F3740GC-UEU-AX
Manufacturer:
NEC
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Part Number:
UPD70F3740GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3740GC-UEU-AX
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V850ES/JG3
communication reservation can be made by setting the IICCn.STTn bit to 1 before a stop condition is detected (n = 0 to 2).
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
SDA0n
SCL0n
Communication reservations are accepted via the following timing.
Remark
Remark
SDA0n
Hardware processing
1
SCL0n
Program processing
SPDn
STDn
n = 0 to 2
2
n = 0 to 2
STTn:
STDn:
SPDn:
3
Figure 17-16. Timing for Accepting Communication Reservations
Bit of IICCn register
Bit of IICSn register
Bit of IICSn register
4
Communication
reservation
STTn
= 1
Figure 17-15. Communication Reservation Timing
5
6
7
Standby mode
8
Generated by master with bus access
9
Set SPDn
and INTIICn
Write to
IICn
Set
STDn
After the IICSn.STDn bit is set to 1, a
1
2
3
CHAPTER 17 I
4
5
Page 593 of 870
6
2
C BUS

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