UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 275

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(2) Operation timing in free-running timer mode
(a) Interval operation with compare register
When 16-bit timer/event counter P is used as an interval timer with the TPnCCRm register used as a compare
register, software processing is necessary for setting a comparison value to generate the next interrupt request
signal each time the INTTPnCCm signal has been detected.
When performing an interval operation in the free-running timer mode, two intervals can be set with one
channel.
To perform the interval operation, the value of the corresponding TPnCCRm register must be re-set in the
interrupt servicing that is executed when the INTTPnCCm signal is detected.
The set value for re-setting the TPnCCRm register can be calculated by the following expression, where “D
the interval period.
Remark
Compare register default value: D
Value set to compare register second and subsequent time: Previous set value + D
(If the calculation result is greater than FFFFH, subtract 10000H from the result and set this value to the
register.)
INTTPnCC0 signal
INTTPnCC1 signal
TPnCCR0 register
TPnCCR1 register
TOPn1 pin output
TOPn pin output
16-bit counter
TPnCE bit
n = 0 to 5
m = 0, 1
FFFFH
0000H
Interval period
Interval period
D
(D
(D
00
00
D
10
m
D
+ 1)
10
+ 1)
D
00
− 1
10
Interval period
CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
(10000H +
D
01
Interval period
− D
(10000H +
D
D
D
00
11
01
)
01
− D
D
Interval period
10
D
11
(D
)
11
02
− D
D
Interval period
02
01
D
(10000H +
)
D
02
12
Interval period
− D
(10000H +
D
D
D
11
03
12
)
12
− D
D
03
02
D
)
Interval period
03
(10000H +
D
Interval period
13
(10000H +
D
− D
04
D
− D
12
D
13
)
D
13
03
04
)
m
D
04
D
D
14
05
Page 259 of 870
m
” is