UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 315

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
TQ0IOC0
(c) TMQ0 I/O control register 0 (TQ0IOC0)
(d) TMQ0 counter read buffer register (TQ0CNT)
(e) TMQ0 capture/compare register 0 (TQ0CCR0)
(f) TMQ0 capture/compare registers 1 to 3 (TQ0CCR1 to TQ0CCR3)
By reading the TQ0CNT register, the count value of the 16-bit counter can be read.
If the TQ0CCR0 register is set to D
Interval = (D
Usually, the TQ0CCR1 to TQ0CCR3 registers are not used in the interval timer mode. However, the set
value of the TQ0CCR1 to TQ0CCR3 registers are transferred to the CCR1 to CCR3 buffer registers. The
compare match interrupt request signals (INTTQ0CC1 to INTTQ0CCR3) is generated when the count
value of the 16-bit counter matches the value of the CCR1 to CCR3 buffer registers.
Therefore, mask the interrupt request by using the corresponding interrupt mask flags (TQ0CCMK1 to
TQ0CCMK3).
Remark
TQ0OL3
0/1
TQ0OE3 TQ0OL2 TQ0OE2
TMQ0 I/O control register 1 (TQ0IOC1), TMQ0 I/O control register 2 (TQ0IOC2), and TMQ0
option register 0 (TQ0OPT0) are not used in the interval timer mode.
0
0/1
Figure 8-4. Register Setting for Interval Timer Mode Operation (2/2)
+ 1) × Count clock cycle
0/1
0/1
0
, the interval is as follows.
TQ0OL1
0/1
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
TQ0OE1 TQ0OL0 TQ0OE0
0/1
0/1
0/1
0: Disable TOQ00 pin output
1: Enable TOQ00 pin output
Setting of output level with
operation of TOQ00 pin disabled
0: Low level
1: High level
0: Disable TOQ01 pin output
1: Enable TOQ01 pin output
Setting of output level with
operation of TOQ01 pin disabled
0: Low level
1: High level
0: Disable TOQ02 pin output
1: Enable TOQ02 pin output
0: Disable TOQ03 pin output
1: Enable TOQ03 pin output
Setting of output level with
operation of TOQ03 pin disabled
0: Low level
1: High level
Setting of output level with
operation of TOQ02 pin disabled
0: Low level
1: High level
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