UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 647

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(4) DMA transfer initialization procedure (setting DCHCn.INITn bit to 1)
Even if the INITn bit is set to 1 when the channel executing DMA transfer is to be initialized, the channel may not
be initialized. To accurately initialize the channel, execute either of the following two procedures.
(a) Temporarily stop transfer of all DMA channels
Initialize the channel executing DMA transfer using the procedure in <1> to <7> below.
Note, however, that TCn bit is cleared to 0 when step <5> is executed. Make sure that the other processing
programs do not expect that the TCn bit is 1.
<1> Disable interrupts (DI).
<2> Read the DCHCn.Enn bit of DMA channels other than the one to be forcibly terminated, and transfer the
<3> Clear the Enn bit of the DMA channels used (including the channel to be forcibly terminated) to 0. To
<4> Write DCHCn = 04H to the channel to be forcibly terminated (set the INITn bit to 1).
<5> Read the TCn bit of each channel not to be forcibly terminated. If both the TCn bit and the Enn bit read in
<6> After the operation in <5>, write the Enn bit value to the DCHCn register.
<7> Enable interrupts (EI).
Cautions 1. Be sure to execute step <5> above to prevent illegal setting of the Enn bit of the channels
value to a general-purpose register.
clear the Enn bit of the last DMA channel, execute the clear instruction twice. If the target of DMA transfer
(transfer source/destination) is the internal RAM, execute the instruction three times.
<2> are 1 (logical product (AND) is 1), clear the saved Enn bit to 0.
Example: Execute instructions in the following order if channels 0, 1, and 2 are used (if the target of
2. When a bit manipulation instruction is used, steps <3> and <4> (Enn bit clear (0) and
whose DMA transfer has been normally completed between <2> and <3>.
INITn bit set (1)) are prohibited because the TCn bit is cleared to 0.
transfer is not the internal RAM).
• Write DCHC0 = 00H (clear the E00 bit to 0)
• Write DCHC1 = 00H (clear the E11 bit to 0)
• Write DCHC2 = 00H (clear the E22 bit to 0)
• Write DCHC2 = 00H again (clear the E22 bit to 0)
CHAPTER 18 DMA FUNCTION (DMA CONTROLLER)
Page 631 of 870