UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 884

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Electrical
specifica-
tions
Function
Subclock
oscillator
characteristics
Data retention
characteristics
AC
characteristics
Bus timing
(multiplexed
bus mode)
Bus timing
(separate bus
mode)
I
A/D converter
2
C bus mode
Details of
Function
When using the subclock oscillator, wire as follows in the area enclosed by the
broken lines in the above figures to avoid an adverse effect from wiring
capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating
• Always make the ground point of the oscillator capacitor the same potential as
• Do not ground the capacitor to a ground pattern through which a high current
• Do not fetch signals from the oscillator.
The subclock oscillator is designed as a low-amplitude circuit for reducing power
consumption, and is more prone to malfunction due to noise than the main clock
oscillator.
Particular care is therefore required with the wiring method when the subclock is
used.
For the resonator selection and oscillator constant, customers are requested to
either evaluate the oscillation themselves or apply to the resonator manufacturer
for evaluation.
Shifting to STOP mode and restoring from STOP mode must be performed within
the rated operating range.
If the load capacitance exceeds 50 pF due to the circuit configuration, bring the
load capacitance of the device to 50 pF or less by inserting a buffer or by some
other means.
When operating at f
setup waits.
When operating at f
setup waits, and data waits.
The address may be changed during the low-level period of the RD pin. To avoid
the address change, insert an address wait.
At the start condition, the first clock pulse is generated after the hold time.
The system requires a minimum of 300 ns hold time internally for the SDA0n
signal (at V
falling edge of SCL0n.
If the system does not extend the SCL0n signal low hold time (t
maximum data hold time (t
The high-speed mode I
this case, set the high-speed mode I
conditions.
• If the system does not extend the SCL0n signal’s low state hold time:
• If the system extends the SCL0n signal’s low state hold time:
Do not set (read/write) alternate-function ports during A/D conversion; otherwise
the conversion resolution may be degraded.
current flows.
V
flows.
t
Transmit the following data bit to the SDA0n line prior to the SCL0n line release
(t
SU:DAT
SS
Rmax
.
. + t
≥ 250 ns
SU:DAT
IHmin
. of SCL0n signal) in order to occupy the undefined area at the
= 1,000 + 250 = 1,250 ns: Normal mode I
XX
XX
> 20 MHz, be sure to insert address hold waits and address
> 20 MHz, be sure to insert address hold waits, address
2
C bus can be used in the normal-mode I
HD:DAT
) needs to be satisfied.
2
Cautions
C bus so that it meets the following
APPENDIX E LIST OF CAUTIONS
2
C bus specification).
LOW
2
C bus system. In
), only the
Page 868 of 870
p. 770
p. 770
p. 770
p. 775
p. 776
p. 778
p. 783
p. 783
p. 794
p. 794
p. 794
p. 794
p. 795
Page
(35/36)