UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 810

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
I
Notes 1. At the start condition, the first clock pulse is generated after the hold time.
Remark n = 0 to 2
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
2
SCL0n clock frequency
Bus free time
(Between start and stop conditions)
Hold time
SCL0n clock low-level width
SCL0n clock high-level width
Setup time for start/restart conditions
Data hold time
Data setup time
SDA0n and SCL0n signal rise time
SDA0n and SCL0n signal fall time
Stop condition setup time
Pulse width of spike suppressed by
input filter
Capacitance load of each bus line
C Bus Mode (T
2. The system requires a minimum of 300 ns hold time internally for the SDA0n signal (at V
3. If the system does not extend the SCL0n signal low hold time (t
4. The high-speed mode I
5. Cb: Total capacitance of one bus line (unit: pF)
Note 1
in order to occupy the undefined area at the falling edge of SCL0n.
(t
high-speed mode I
• If the system does not extend the SCL0n signal’s low state hold time:
• If the system extends the SCL0n signal’s low state hold time:
HD
Parameter
t
Transmit the following data bit to the SDA0n line prior to the SCL0n line release (t
250 = 1,250 ns: Normal mode I
:
DAT
SU
CBUS compatible
master
I
A
2
:
C mode
DAT
) needs to be satisfied.
= −40 to +85°C, V
≥ 250 ns
2
C bus so that it meets the following conditions.
DD
2
f
t
t
t
t
t
t
t
t
t
t
t
Cb
C bus can be used in the normal-mode I
CLK
BUF
HD: STA
LOW
HIGH
SU: STA
HD: DAT
SU: DAT
R
F
SU: STO
SP
= EV
Symbol
DD
<99>
<100>
<101>
<102>
<103>
<104>
<105>
<106>
<107>
<108>
<109>
2
= AV
C bus specification).
REF0
= AV
MIN.
0
250
4.7
4.0
4.7
4.0
4.7
5.0
4.0
Note 2
0
−
−
−
−
Normal Mode
CHAPTER 29
REF1
, V
SS
= EV
MAX.
1000
100
300
400
−
−
−
−
−
−
−
−
−
−
SS
= AV
LOW
20 + 0.1Cb
20 + 0.1Cb
ELECTRICAL SPECIFICATIONS
SS
2
C bus system. In this case, set the
), only the maximum data hold time
100
= 0 V, C
MIN.
0
1.3
0.6
1.3
0.6
0.6
0.6
High-Speed Mode
Note 2
0
−
0
−
Note 4
Note 5
Note 5
L
= 50 pF)
Rmax.
0.9
MAX.
400
300
300
400
IHmin.
50
−
−
−
−
−
−
−
−
Note 3
+ t
of SCL0n signal)
Page 794 of 870
SU:DAT
= 1,000 +
Unit
kHz
pF
μ
μ
μ
μ
μ
μ
μ
ns
ns
ns
μ
ns
s
s
s
s
s
s
s
s