UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 844

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
DBTRAP
DI
DISPOSE
DIV
DIVH
DIVHU
DIVU
EI
HALT
HSW
JARL
JMP
JR
LD.B
LD.BU
Mnemonic
imm5,list12
imm5,list12,[reg1]
reg1,reg2,reg3
reg1,reg2
reg1,reg2,reg3
reg1,reg2,reg3
reg1,reg2,reg3
reg2,reg3
disp22,reg2
[reg1]
disp22
disp16[reg1],reg2
disp16[reg1],reg2
Operand
1111100001000000
0000011111100000
0000000101100000
0 0 0 0 0 1 1 0 0 1 i i i i i L
LLLLLLLLLLL00000
0 0 0 0 0 1 1 0 0 1 i i i i i L
LLLLLLLLLLLRRRRR
r r rr r1 11 11 1 RRRRR
wwwww01011000000
r r rr r0 00 01 0 RRRRR GR[reg2]←GR[reg2]÷GR[reg1]
r r rr r1 11 11 1 RRRRR
wwwww01010000000
r r rr r1 11 11 1 RRRRR
wwwww01010000010
r r rr r1 11 11 1 RRRRR
wwwww01011000010
1000011111100000
0000000101100000
0000011111100000
0000000100100000
r r r r r 1 1 1 1 1 1 0 0 0 0 0
wwwww01101000100
r r r r r 1 1 1 1 0 d d d d d d
ddddddddddddddd0
00000000011RRRRR PC←GR[reg1]
0000011110dddddd
ddddddddddddddd0
r r rr r1 11 00 0 RRRRR
dddddddddddddddd
r r rr r1 11 10 b RRRRR
dddddddddddddd1
Opcode
Notes 8, 10
Note 5
Note 7
Note 7
DBPC←PC+2 (restored PC)
DBPSW←PSW
PSW.NP←1
PSW.EP←1
PSW.ID←1
PC←00000060H
PSW.ID←1
sp←sp+zero-extend(imm5 logically shift left by 2)
GR[reg in list12]←Load-memory(sp,Word)
sp←sp+4
repeat 2 steps above until all regs in list12 is loaded
sp←sp+zero-extend(imm5 logically shift left by 2)
GR[reg in list12]←Load-memory(sp,Word)
sp←sp+4
repeat 2 steps above until all regs in list12 is loaded
PC←GR[reg1]
GR[reg2]←GR[reg2]÷GR[reg1]
GR[reg3]←GR[reg2]%GR[reg1]
GR[reg2]←GR[reg2]÷GR[reg1]
GR[reg3]←GR[reg2]%GR[reg1]
GR[reg2]←GR[reg2]÷GR[reg1]
GR[reg3]←GR[reg2]%GR[reg1]
GR[reg2]←GR[reg2]÷GR[reg1]
GR[reg3]←GR[reg2]%GR[reg1]
PSW.ID←0
Stop
GR[reg3]←GR[reg2](15 : 0) ll GR[reg2] (31 : 16)
GR[reg2]←PC+4
PC←PC+sign-extend(disp22)
PC←PC+sign-extend(disp22)
adr←GR[reg1]+sign-extend(disp16)
GR[reg2]←sign-extend(Load-memory(adr,Byte))
adr←GR[reg1]+sign-extend(disp16)
GR[reg2]←zero-extend(Load-memory(adr,Byte))
Operation
Note 6
Note 6
Note 6
APPENDIX D INSTRUCTION SET LIST
n+1
Note 4
n+3
Note 4
35 35 35
35 35 35
35 35 35
34 34 34
34 34 34
3
1
1
1
1
2
3
2
1
1
Execution
i
Clock
Note 4
Note 4
n+1
n+3
3
1
1
1
1
2
3
2
1
1
r
n+1
Note 4
n+3
Note 4
Note
Note
11
11
3
1
1
1
1
2
3
2
l
CY OV S
×
×
×
×
×
×
0
Page 828 of 870
Flags
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Z SAT
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