UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 745

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
For details, refer to the PG-FP4 User’s Manual (U15260E).
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Signal Name
FLMD0
FLMD1
VDD
GND
CLK
RESET
SI/RxD
SO/TxD
SCK
HS
(3) CSIB0 + HS, CSIB3 + HS
The dedicated flash programmer outputs the transfer clock, and the V850ES/JG3 operates as a slave.
When the PG-FP4 is used as the dedicated flash programmer, it generates the following signals to the V850ES/JG3.
Notes 1. Wire these pins as shown in Figure 27-6, or connect then to GND via pull-down resistor on board.
Remark
Note Connect the FLMD1 pin to the flash programmer or connect to a GND via a pull-down resistor on the board.
Serial clock: 2.4 kHz to 2.5 MHz (MSB first)
2. Clock cannot be supplied via the CLK pin of the flash programmer. Create an oscillator on board and supply
Figure 27-5. Communication with Dedicated Flash Programmer (CSIB0 + HS, CSIB3 + HS)
the clock.
×: Does not have to be connected.
Output
Output
Output
Output
Input
Output
Output
Input
: Must be connected.
I/O
−
−
Table 27-5. Signal Connections of Dedicated Flash Programmer (PG-FP4)
Dedicated flash
Write enable/disable
Write enable/disable
V
Ground
Clock output to V850ES/JG3
Reset signal
Receive signal
Transmit signal
Transfer clock
Handshake signal for CSIB0 + HS, CSIB3
+ HS communication
DD
programmer
PG-FP4
voltage generation/voltage monitor
Pin Function
RESET
FLMD0
FLMD1
GND
SCK
V
SO
HS
SI
DD
FLMD0
FLMD1
V
V
X1, X2
RESET
SOB0, SOB3/
TXDA0
SIB0, SIB3/
RXDA0
SCKB0, SCKB3
PCM0
DD
SS
V850ES/JG3
FLMD0
Pin Name
FLMD1
V
RESET
SOB0, SOB3
SIB0, SIB3
SCKB0, SCKB3
PCM0
V
SS
DD
Note
UARTA0
CHAPTER 27 FLASH MEMORY
V850ES/JG3
×
Note 2
Note 1
×
×
Processing for Connection
CSIB0,
CSIB3
×
Note 2
Note 1
×
CSIB0 + HS,
CSIB3 + HS
Page 729 of 870
×
Note 2
Note 1