UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 580

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
wait state is canceled and the transmitting side writes data to the IICn register to cancel the wait state.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
A wait state may be automatically generated depending on the setting of the IICCn.WTIMn bit (n = 0 to 2).
Normally, when the IICCn.WRELn bit is set to 1 or when FFH is written to the IICn register on the receiving side, the
The master device can also cancel the wait state via either of the following methods.
• By setting the IICCn.STTn bit to 1
• By setting the IICCn.SPTn bit to 1
Remark
Transfer lines
Master
Slave
n = 0 to 2
ACKEn
SDA0n
SCL0n
SCL0n
SCL0n
IICn
IICn
(b) When master and slave devices both have a nine-clock wait
(master: transmission, slave: reception, and ACKEn bit = 1)
Generated according to previously set ACKEn bit value
H
D2
6
6
D1
7
7
Figure 17-13. Wait State (2/2)
Master and slave both wait
after output of ninth clock.
D0
8
8
ACK
9
9
Wait state
from master/
slave
IICn data write (cancel wait state)
1
Wait state
from slave
D7
FFH is written to IICn register
or WRELn bit is set to 1.
1
D6
2
2
D5
CHAPTER 17 I
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C BUS