UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 695

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Item
Main clock oscillator
Subclock oscillator
Internal oscillator
PLL
CPU
DMA
Interrupt controller
Timer P (TMP0 to TMP5)
Timer Q (TMQ0)
Timer M (TMM0)
Watch timer
Watchdog timer 2
Serial interface
A/D converter
D/A converter
Real-time output function (RTO)
Key interrupt function (KR)
CRC operation circuit
External bus interface
Port function
Internal data
(2) Releasing HALT mode by reset
The same operation as the normal reset operation is performed.
Setting of HALT Mode
CSIB0 to CSIB4
I
UARTA0 to UARTA2
2
C00 to I
2
C02
Table 21-3. Operating Status in HALT Mode
Oscillation enabled
Oscillation enabled
Operable
Stops operation
Operable
Operable
Operable
Operable
Operable when a clock other than f
selected as the count clock
Operable when f
selected as the count clock
Operable when a clock other than f
selected as the count clock
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable (No data input to the CRCIN register because the CPU is stopped)
See 2.2 Pin States.
Retains status before HALT mode was set
The CPU registers, statuses, data, and all other internal data such as the contents of
the internal RAM are retained as they were before the HALT mode was set.
When Subclock Is Not Used
X
(divided BRG) is
−
Operating Status
XT
XT
is
is
CHAPTER 21 STANDBY FUNCTION
Oscillation enabled
Operable
Operable
Operable
When Subclock Is Used
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