UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 480

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
15.6.3 SBF transmission
transmission is started by setting (to 1) the SBF transmission trigger (UAnOPT0.UAnSTT bit).
output. A transmission enable interrupt request signal (INTUAnT) is generated upon SBF transmission start. Following the
end of SBF transmission, the UAnSTT bit is automatically cleared. Thereafter, the UART transmission mode is restored.
transmission trigger (UAnSTT bit) is set.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
When the UAnCTL0.UAnPWR bit = UAnCTL0.UAnTXE bit = 1, the transmission enabled status is entered, and SBF
Thereafter, a low level the width of bits 13 to 20 specified by the UAnOPT0.UAnSLS2 to UAnOPT0.UAnSLS0 bits is
Transmission is suspended until the data to be transmitted next is written to the UAnTX register, or until the SBF
TXDAn
INTUAnT
interrupt
Setting of UAnSTT bit
1
2
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
3
Figure 15-8. SBF Transmission
4
5
6
7
8
9
10
11
12
13
Stop
bit
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