UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 251

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOPn1 pin. After the
one-shot pulse is output, the 16-bit counter is set to FFFFH, stops counting, and waits for a trigger. If a trigger is
generated again while the one-shot pulse is being output, it is ignored.
value matches the value of the CCR0 buffer register. The compare match interrupt request signal INTTPnCC1 is
generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register.
trigger.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
When the TPnCE bit is set to 1, 16-bit timer/event counter P waits for a trigger. When the trigger is generated, the 16-
The output delay period and active level width of the one-shot pulse can be calculated as follows.
The compare match interrupt request signal INTTPnCC0 is generated when the 16-bit counter counts after its count
The valid edge of an external trigger input or setting the software trigger (TPnCTL1.TPnEST bit) to 1 is used as the
Remark
External trigger input
(only when software
Output delay period = (Set value of TPnCCR1 register) × Count clock cycle
Active level width = (Set value of TPnCCR0 register − Set value of TPnCCR1 register + 1) × Count clock cycle
INTTPnCC0 signal
INTTPnCC1 signal
TPnCCR0 register
TPnCCR1 register
TOPn0 pin output
TOPn1 pin output
(TIPn0 pin input)
trigger is used)
16-bit counter
n = 0 to 5
m = 0, 1
TPnCE bit
FFFFH
0000H
Figure 7-21. Basic Timing in One-Shot Pulse Output Mode
Delay
(D
D
1
1
)
Active
level width
(D
D
0
0
− D
1
CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
+ 1)
Delay
(D
D
1
1
)
Active
level width
(D
D
D
D
0
0
0
1
− D
1
+ 1)
Delay
(D
D
1
1
)
Active
level width
(D
D
0
0
− D
1
+ 1)
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