UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 671

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
19.3.6 In-service priority register (ISPR)
signal is acknowledged, the bit of this register corresponding to the priority level of that interrupt request signal is set to 1
and remains set while the interrupt is serviced.
automatically reset to 0 by hardware. However, it is not reset to 0 when execution is returned from non-maskable interrupt
servicing or exception processing.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
The ISPR register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request
When the RETI instruction is executed, the bit corresponding to the interrupt request signal having the highest priority is
This register is read-only, in 8-bit or 1-bit units.
Reset sets this register to 00H.
Caution If an interrupt is acknowledged while the ISPR register is being read in the interrupt enabled (EI)
Remark
status, the value of the ISPR register after the bits of the register have been set by acknowledging the
interrupt may be read. To accurately read the value of the ISPR register before an interrupt is
acknowledged, read the register while interrupts are disabled (DI).
n = 0 to 7 (priority level)
After reset:
ISPR
ISPRn
ISPR7
00H
<7>
0
1
Interrupt request signal with priority n not acknowledged
Interrupt request signal with priority n acknowledged
R
ISPR6
<6>
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Address:
ISPR5
<5>
Priority of interrupt currently acknowledged
FFFFF1FAH
ISPR4
<4>
ISPR3
<3>
ISPR2
<2>
ISPR1
<1>
ISPR0
<0>
Page 655 of 870