UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 660

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
19.3 Maskable Interrupts
interrupt sources.
the default priority. In addition to the default priority, eight levels of priorities can be specified by using the interrupt control
registers (programmable priority control).
signals is disabled and the interrupt disabled (DI) status is set.
enables servicing of interrupts having a higher priority than the interrupt request signal in progress (specified by the
interrupt control register). Note that only interrupts with a higher priority will have this capability; interrupts with the same
priority level cannot be nested.
executing the EI instruction, and execute the DI instruction before the RETI instruction to restore the original values of
EIPC and EIPSW.
19.3.1 Operation
another interrupt is being serviced (while the PSW.NP bit = 1 or the PSW.ID bit = 1) are held pending inside INTC. In this
case, servicing a new maskable interrupt is started in accordance with the priority of the pending maskable interrupt
request signal if either the maskable interrupt is unmasked or the NP and ID bits are cleared to 0 by using the RETI or
LDSR instruction.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Maskable interrupt request signals can be masked by interrupt control registers. The V850ES/JG3 has 55 maskable
If two or more maskable interrupt request signals are generated at the same time, they are acknowledged according to
When an interrupt request signal has been acknowledged, the acknowledgment of other maskable interrupt request
When the EI instruction is executed in an interrupt service routine, the interrupt enabled (EI) status is set, which
To enable multiple interrupts, however, save EIPC and EIPSW to memory or general-purpose registers before
If a maskable interrupt occurs, the CPU performs the following processing, and transfers control to a handler routine.
<1> Saves the restored PC to EIPC.
<2> Saves the current PSW to EIPSW.
<3> Writes an exception code to the lower halfword of ECR (EICC).
<4> Sets the PSW. ID bit to 1 and clears the PSW. EP bit to 0.
<5> Sets the handler address corresponding to each interrupt to the PC, and transfers control.
The maskable interrupt request signal masked by INTC and the maskable interrupt request signal generated while
How maskable interrupts are serviced is illustrated below.
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
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